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D a t a S he et , V 1. 0 2 , M a y 2 0 0 4
H Y B 1 8 T 1 G 4 00 A F H Y B 1 8 T 1 G 8 00 A F H Y B 1 8 T 1 G 1 60 A F
1 G b i t D D R 2 S D R AM
M e m o r y P r o d u c ts
Never
stop
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Edition 2004-05-03 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 Munchen, Germany (c) Infineon Technologies AG 5/7/04. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
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HYB18T1G400/800/160AF
DATASHEET Rev. 1.02 (05.04)
Features * High Performance:
-5 -400 -3.7 -533 -3S -667 -3
1Gb DDR2 SDRAM
Speed Sorts DDR2 DDR2 DDR2 DDR2
-667
Units tck MHz Mb/s/pin
Bin (CL-tRCD-TRP)
max. Clock Frequency
3-3-3 4-4-4 5-5-5 4-4-4 200 400 3 15 15 40 55 266 533 4 15 15 45 60 5 15 15 45 60 333 667 4 12 12 45 57
Data Rate CAS Latency (CL) tRCD tRP tRAS tRC
tck ns ns ns ns
* 1.8V 0.1V Power Supply 1.8 V 0.1V (SSTL_18) compatible) I/O * DRAM organisations with 4, 8 and 16 data in/outputs * Double Data Rate architecture: two data transfers per clock cycle, eight internal banks for concurrent operation * CAS Latency: 3, 4 and 5 * Burst Length: 4 and 8
* Differential clock inputs (CK and CK) * Bi-directional, differential data strobes (DQS and DQS) are transmitted / received with data. Edge aligned with read data and center-aligned with write data * DLL aligns DQ and DQS transitions with clock * DQS can be disabled for single-ended data strobe operation * Commands entered on each positive clock edge, data and data mask are referenced to both edges of DQS * Data masks (DM) for write data * Posted CAS by programmable additive latency for better command and data bus efficiency * Off-Chip-Driver impedance adjustment (OCD) and On-DieTermination (ODT) for better signal quality. * Auto-Precharge operation for read and write bursts * Auto-Refresh, Self-Refresh and power saving PowerDown modes * Average Refresh Period 7.8s at a TCASE lower than 85oC, 3.9s between 85oC and 95oC * Strong and Weak Strength Data-Output Driver * 1k page size for x 4 & x 8, 2k page size for x16
* Lead-free Packages:
68 pin FBGA for x4 & x8 components 92 pin FBGA for x16 components
1.0 Description
The 1Gb Double-Data-Rate-2 (DDR2) DRAMs are high-speed CMOS Double Data Rate 2 Synchronous DRAM devices containing 1,073,741,824 bits and is internally configured as a octal-bank DRAM. The 1Gb chip is organized as either 32Mbit x 4 I/O x 8 banks, 16Mbit x 8 I/O x 8 banks or 8Mbit x 16 I/O x 8 banks device. These synchronous devices achieve high speed double-data-rate transfer rates of up to 667 Mb/sec/pin for general applications. The chip is designed to comply with all key DDR2 DRAM key features: (1) posted CAS with additive latency, (2) write latency = read latency -1, (3) normal and weak strength data-output driver, (4) Off-Chip Driver (OCD) impedance adjustment and (5) an ODT (On-Die Termination) function. All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a single ended DQS or differential (DQS, DQS) pair in a source synchronous fashion. A 17 bit address bus for x 4 and x 8 organised components and a 16 bit address bus for x16 components is used to convey row, column and bank address information in a RAS / CAS multiplexing style. The DDR2 devices operate with a 1.8V +/-0.1V power supply and are available in FBGA packages. An Auto-Refresh and Self-Refresh mode is provided along with various power-saving power-down modes. The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation.
Page 3
Rainer.Weidlich@Infineon.com
Rev. 1.02 May 2004
INFINEON Technologies
HYB18T1G400/800/160AF
1Gb DDR2 SDRAM
1.1 Ordering Information
Part Number HYB18T1G400AF(L)-5 HYB18T1G800AF(L)-5 HYB18T1G160AF(L)-5 HYB18T1G400AF(L)-3.7 HYB18T1G800AF(L)-3.7 HYB18T1G160AF(L)-3.7 HYB18T1G400AF(L)-3 HYB18T1G800AF(L)-3 HYB18T1G160AF(L)-3 HYB18T1G400AF(L)-3S HYB18T1G800AF(L)-3S HYB18T1G160AF(L)-3S 4&5 333 DDR2-667 4&5 266 DDR2-533 3, 4 & 5 200 DDR2-400 CAS Latency Clock (MHz) Speed Sort DRAM Organisation 8 banks x 32 Mbits x 4 8 banks x 16 Mbits x 8 8 banks x 8 Mbits x 16 8 banks x 32 Mbits x 4 8 banks x 16 Mbits x 8 8 banks x 8 Mbits x 16 8 banks x 32 Mbits x 4 8 banks x 16 Mbits x 8 8 banks x 8 Mbits x 16 8 banks x 32 Mbits x 4 8 banks x 16 Mbits x 8 8 banks x 8 Mbits x 16 Package 68 pin FBGA 68 pin FBGA 92 pin FBGA 68 pin FBGA 68 pin FBGA 92 pin FBGA 68 pin FBGA 68 pin FBGA 92 pin FBGA 68 pin FBGA 68 pin FBGA 92 pin FBGA
5
Notes: 1) For product nomenclature see section 10 of this datasheet 2) Versions with an "L" in the part numbers are Low Power versions of the standard component with reduced IDD6 Self-Refresh current. See section 6.1 for IDD current specifications. 3.)All FBGA packages are lead-free.
1.2 Pin Description
1.2.1 x4 Components
Symbol A0~A13 A0~A9,A11 BA0, BA1, BA2 A10/AP CS RAS CAS WE DQ0~DQ3 CKE CK, CK DM Function Row Address Inputs Column Address Inputs Bank Address Inputs Column Address Input for Auto-Precharge Chip Select Row Address Strobe Column Address Strobe Write Enable Data Inputs/Outputs (x4) Clock Enable Differential Clock Inputs Data Input Mask Symbol DQS, DQS NC VDD VSS VDDQ VSSQ VDDL VSSDL VREF ODT NC Function Differential Data Strobes No Connection (Chip to Pin) Supply Voltage Ground Supply Voltage for DQ Ground for DQs Supply Voltage for DLL Ground for DLL Reference Voltage for SSTL Inputs On Die Termination Enable Not connected
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Rev. 1.02
May 2004
INFINEON Technologies
HYB18T1G400/800/160AF
1Gb DDR2 SDRAM
1.2.1 x8 Components
Symbol A0~A13 A0~A9 BA0, BA1, BA2 A10/AP CS RAS CAS WE DQ0~DQ7 CKE CK, CK DM Function Row Address Inputs Column Address Inputs Bank Address Inputs Column Address Input for Auto-Precharge Chip Select Row Address Strobe Column Address Strobe Write Enable Data Inputs/Outputs (x8) Clock Enable Differential Clock Inputs Data Input Mask Symbol DQS, DQS RDQS, RDQS VDD VSS VDDQ VSSQ VDDL VSSDL VREF ODT NC Function Differential Data Strobes Differential Read Data Strobes Supply Voltage Ground Supply Voltage for DQ Ground for DQs Supply Voltage for DLL Ground for DLL Reference Voltage for SSTL Inputs On Die Termination Enable Not connected
1.2.3 x16 Components
Symbol A0~A12 A0~A9 BA0, BA1, BA2 A10/AP CS RAS CAS WE LDQ0~7, UDQ0~7 CKE CK, CK LDM, UDM Function Row Address Inputs Column Address Inputs Bank Address Inputs Column Address Input for Auto-Precharge Chip Select Row Address Strobe Column Address Strobe Write Enable Data Inputs/Outputs Clock Enable Differential Clock Inputs Data Input Masks Symbol LDQS,LDQS UDQS,UDQS NC VDD VSS VDDQ VSSQ VDDL VSSDL VREF ODT NC Function Differential Data Strobes No Connection (Chip to Pin) Supply Voltage Ground Supply Voltage for DQ Ground for DQs Supply Voltage for DLL Ground for DLL Reference Voltage for SSTL Inputs On Die Termination Enable Not connected
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Rev. 1.02
May 2004
INFINEON Technologies
HYB18T1G400/800/160AF
1Gb DDR2 SDRAM
1.3 1Gbit DDR2 Addressing
Configuration # of Banks Bank Address Auto-Precharge Row Address Column Address Page Length Page Size 256Mb x 4 8 BA0, BA1, BA2 A10 / AP A0 ~ A13 A0 ~ A9, A11 2048 bits 1024 (1kB) 128Mb x 8 8 BA0, BA1, BA2 A10 / AP A0 ~ A13 A0 ~ A9 1024 bits 1024 (1kB) 64Mb x 16 8 BA0, BA1, BA2 A10 / AP A0 ~ A12 A0 ~ A9 1024 bits 2048 (2kB)
page length = 2 colbit,, page size in bytes = 2 colbits x ORG / 8 where colbits is the number of column address bits and ORG the number of I/O (DQ) bits.
1.4 Package Pinout & Addressing
1.4.1 Package Pinout for x4 components, 60 pins + 8 support pins, FBGA-68 Package (top view)
1 NC
2 NC
3 A B C D
7
8 NC
9 NC
VDD NC VDDQ NC VDDL
NC VSSQ DQ1 VSSQ VREF CKE
VSS DM VDDQ DQ3 VSS WE BA1 A1 A5 A9 NC(A14)
E F G H J K L M N P R T U V
VSSQ DQS VDDQ DQ2 VSSDL RAS CAS A2 A6 A11 NC,(A15)
DQS VSSQ DQ0 VSSQ CK CK CS A0 A4 A8 A13
VDDQ NC VDDQ NC VDD ODT
BA2
BA0 A10
VDD
VSS
A3 A7
VSS
VDD
A12
NC
NC
W
NC
NC
Notes: 1) VDDL and VSSDL are power and ground for the DLL.They are isolated on the device from VDD, VDDQ, VSS and VSSQ. 2) NC, (A14) andNC, (A15) are additional address pins for future generation DRAMs and are not connected on this component.
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Rev. 1.02
May 2004
INFINEON Technologies
HYB18T1G400/800/160AF
1Gb DDR2 SDRAM
1.4.2 Package Pinout for x8 components, 60 pins + 8 support pins, FBGA-68 Package (top view)
1 NC
2 NC
3 A B C D
7
8 NC
9 NC
VDD DQ6 VDDQ DQ4 VDDL
NU, RDQS VSSQ DQ1 VSSQ VREF CKE
VSS DM, RDQS VDDQ DQ3 VSS WE BA1 A1 A5 A9 NC,(A14)
E F G H J K L M N P R T U V
VSSQ DQS VDDQ DQ2 VSSDL RAS CAS A2 A6 A11 NC,(A15)
DQS VSSQ DQ0 VSSQ CK CK CS A0 A4 A8 A13
VDDQ DQ7 VDDQ DQ5 VDD ODT
BA2
BA0 A10
VDD
VSS
A3 A7
VSS
VDD
A12
NC Notes:
NC
W
NC
NC
1) RDQS / RDQS are enabled by EMRS(1) command. 2) If RDQS / RDQS is enabled, the DM function is disabled 3) When enabled, RDQS & RDQS are used as strobe signals during reads. 4) VDDL and VSSDL are power and ground for the DLL. They are isolated on the device from VDD, VDDQ, VSS and VSSQ. 5) NC,(A14) and NC,(A15) are additional address pins for future generation DRAMs and are not connected on this component.
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Rev. 1.02
May 2004
INFINEON Technologies
HYB18T1G400/800/160AF
1Gb DDR2 SDRAM
1.4.3 Package Pinout for x16 components 84 pins + 8 support pins, FBGA-92 Package (top view)
1 NC
2 NC
3 A B C
7
8 NC
9 NC
VDD UDQ6 VDDQ UDQ4 VDD LDQ6 VDDQ LDQ4 VDDL
NC VSSQ UDQ1 VSSQ NC VSSQ LDQ1 VSSQ VREF CKE
VSS UDM VDDQ DQ3 VSS LDM VDDQ LDQ3 VSS WE BA1 A1 A5 A9 NC,(A14)
D E F G H J K L M N P R T U V W X
VSSQ UDQS VDDQ UDQ2 VSSQ LDQS VDDQ LDQ2 VSSDL RAS CAS A2 A6 A11
UDQS VSSQ UDQ0 VSSQ LDQS VSSQ LDQ0 VSSQ CK CK CS A0 A4 A8
VDDQ UDQ7 VDDQ UDQ5 VDDQ LDQ7 VDDQ LDQ5 VDD ODT
BA2
BA0 A10
VDD
VSS
A3 A7
VSS
VDD
A12
NC,(A15) NC,(A13)
NC Notes:
NC
AA
NC
NC
1) UDQS/UDQS is data strobe for upper byte, LDQS/LDQS is data strobe for lower byte 2) UDM is the data mask signal for the upper byte UDQ0~UDQ7, LDM is the data mask signal for the lower byte LDQ0~LDQ7 3) NC,(A13), NC,(A14) and NC,(A15) are additional address pins for future generation DRAMs and are not connected on this component.
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Rev. 1.02
May 2004
INFINEON Technologies
HYB18T1G400/800/160AF
1Gb DDR2 SDRAM
1.5 Input/Output Functional Description
Symbol CK, CK Type Function Clock: CK and CK are differential system clock inputs. All address and control inputs are sampled on the crossing of Input the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossing of CK and CK (both direction of crossing) Clock Enable: CKE high activates and CKE low deactivates internal clock signals and device input buffers and output drivers. Taking CKE low provides Precharge Power-Down and Self-Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is synchronous for power down entry and exit and for self-refresh entry. Input buffers excluding CKE are disabled during self-refresh. CKE is used asynchronously to detect self-refresh exit Input condition. Self-refresh termination itself is synchronous. After VREF has become stable during power-on and initialisation sequence, it must be maintained for proper operation of the CKE receiver. For proper self-refresh entry and exit, VREF must be maintained to this input. CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, CK, ODT and CKE are disabled during dower-down. Input Chip Select: All command are masked when CS is registered high. CS provides for external rank selection on systems with multiple memory ranks. CS is considered part of the command code.
CKE
CS RAS, CAS, WE
Input Command Inputs: RAS, CAS and WE (along with CS) define the command being entered
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled high coincident with that input data during a Write access. DM is sampled on both edges of DQS. Although DM pins are input DM, LDM, UDM Input only, the DM loading matches the DQ and DQS loading. LDM and UDM are the input mask signals for x16 components and control the lower or upper bytes. For x8 components the data mask function is disabled, when RDQS / RQDS are enabled by EMRS(1) command. BA0, BA1, BA2 Bank Address Inputs: BA0, BA1, BA2 define to which of the 8 internal memory banks an Activate, Read, Write or Input Precharge command is being applied. BA0 and BA1 also determines if the mode register or extended mode register is to be accessed during a MRS or EMRS cycle. Address Inputs: Provides the row address for Activate commands and the column address and Auto-Precharge bit A10 (=AP) for Read/Write commands to select one location out of the memory array in the respective bank. A10 (=AP) is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10=low) Input or all banks (A10=high). If only one bank is to be precharged, the bank is selected by BA0, BA1 and BA2. The address inputs also provide the op-code during Mode Register Set commands. Row address A13 is used on x4 and x8 components only. Input/ Data Inputs/Output: Bi-directional data bus. DQ0~DQ3 for x4 components, DQ0~DQ7 for x8 components, Output LDQ0~LDQ7 and UDQ0~UDQ7 for x16 components
A0 - A13
DQx, LDQx,UDQx
Data Strobe: output with read data, input with write data. Edge aligned with read data, centered with write data. For DQS, (DQS) the x16, LDQS corresponds to the data on LDQ0 - LDQ7; UDQS corresponds to the data on UDQ0-UDQ7. The data LDQS, (LDQS), Input/ strobes DQS, LDQS, UDQS may be used in single ended mode or paired with the optional complementary signals UDQS,(UDQS) Output DQS, LDQS, UDQS to provide differential pair signaling to the system during both reads and writes. An EMRS(1) control bit enables or disables the complementary data strobe signals. RDQS, (RDQS) Read Data Strobe: For the x8 components a RDQS, RDQS pair can be enabled via the EMRS(1) for read timing. Input/ RDQS, RDQS is not supported on x4 and x16 components. RDQS, RDQS are edge-aligned with read data. If Output RDQS, RDQS is enabled, the DM function is disabled on x8 components. Input On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM. When enabled, ODT is applied to each DQ, DQS, DQS and DM signal for x4 and DQ, DQS, DQS, RDQS, RDQS and DM for x8 configurations. For x16 configuration ODT is applied to each DQ, UDQS, UDQS, LDQS, LDQS, UDM and LDM signal. The ODT pin will be ignored if the Extended Mode Register (EMRS(1)) is programmed to disable ODT. No Connect: no internal electrical connection is present Supply DQ Power Supply: 1.8V +/- 0.1V Supply DQ Ground Supply DLL Power Supply: 1.8V +/- 0.1V Supply DLL Ground Supply Power Supply: 1.8V +/- 0.1V Supply Ground Supply Reference Voltage A14 ~ A15 are additional address pins for future generation DRAMs and are not connected on this component.
ODT NC VDDQ VSSQ VDDL VSSDL VDD VSS VREF (A14~A15)
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Rev. 1.02
May 2004
INFINEON Technologies
HYB18T1G400/800/160AF
1Gb DDR2 SDRAM
1.6 Block Diagrams
CKE CK CK CS WE CAS RAS AP
Row-Address MUX Bank0 Row-Address Latch & Decoder
Command Decode
Control Logic
Bank7 Bank1 Bank0 CK, CK DLL
Mode Registers
17
17
16384
Read Latch
Sense Amplifiers
8192
Refresh Counter
8
Bank Control Logic
MUX
16
4 4 4 4
14
4 DQS Generator 2
Drivers
17
Bank0 Memory Array (16384 x 512 x 16)
Data
Address Register
COL0,1 I/O Gating DM Mask Logic 8 512 (x16) Column Decoder 9 16 16 Write FIFO & Drivers
A0-A13, BA0-BA2
2
17
Input Register 1 Mask 1 1 1 4 1 4 16 4 4 4 1 1 1 4 4 4 4 4 1
DQS DQS
DQ0-DQ3, DM DQS DQS
2
11
Column-Address Counter/Latch 2
COL0,1 Data CK, CK
COL0,1
Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does not represent an actual circuit implementation. Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidirectional DQ and DQS signals.
Block Diagram 64Mbit x 4 I/O x 4 Internal Memory Banks, (128 Mbit x 4 Organisation with 14 Row, 3 Bank and 12 Column External Addresses)
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Rev. 1.02
May 2004
INFINEON Technologies
Receivers
HYB18T1G400/800/160AF
1Gb DDR2 SDRAM
CKE CK CK CS WE CAS RAS AP
Command Decode
Control Logic
Bank7 Bank1 Bank0
Row-Address MUX Bank0 Row-Address Latch & Decoder
CK, CK DLL
Mode Registers
17
17
16384
Read Latch
Sense Amplifiers
8192
Refresh Counter
MUX
32
8 8 8 8
8 DQS Generator 1
Bank Control Logic
Drivers
17
Bank0 Memory Array (16384 x256x32)
Data
14
Address Register
8
A0-A13, BA0-BA2
2
17
I/O Gating DM Mask Logic 8
256 (x32)
COL0,1
32
32 Write FIFO & Drivers
Input Register 1 Mask 1 1 1 4 1 8 32 8 8 8 1 1 1 8 8 8 8 8 1
DQS DQS
DQ0-DQ7, DM DQS DQS
2
Column Decoder 8 10 Column-Address Counter/Latch 2
CK, CK
COL0,1
Data
COL0,1
Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does not represent an actual circuit implementation. Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidirectional DQ and DQS signals.
Block Diagram 32Mbit x 8 I/O x 4 Internal Memory Banks (64Mb x 8 Organisation with 14 Row, 3 Bank and 11 Column External Addresses)
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Rev. 1.02
May 2004
INFINEON Technologies
Receivers
HYB18T1G400/800/160AF
1Gb DDR2 SDRAM
CKE CK CK CS WE CAS RAS AP
Command Decode
Control Logic
Bank7 Bank2 Bank1
Row-Address MUX Bank0 Row-Address Latch & Decoder
CK, CK DLL
Mode Registers
16
16
8192
Read Latch
16
13
Sense Amplifiers
16384
MUX
64
Refresh Counter
16 16 16 16
16 DQS Generator 1
Drivers
Bank0 Memory Array (8192 x 256 x 64)
Data
Address Register
8
COL0,1
A0-A12, BA0-BA2
2
16
I/O Gating DM Mask Logic 8
256 (x64)
64
64
2
Write FIFO & Drivers
Input Register 2 Mask 2 2 2 8 2 16 64 16 16 16 2 2 2 16 16 16 16 2
DQS DQS
Column Decoder 8 10 Column-Address Counter/Latch 2
CK, CK
16
COL0
Data
COL0,1
Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does not represent an actual circuit implementation. Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the
Block Diagram 16Mbit x 16 I/O x 4 Internal Memory Banks (32Mb x 16 Organisation with 13 Row, 3 Bank and 11 Column External Addresses)
Receivers
LDQ0-LDQ7 LDM UDQ0-UDQ7 UDM LDQS LDQS UDQS UDQS
Bank Control Logic
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Rev. 1.02
May 2004
INFINEON Technologies
HYB18T1G400/800/160AF
1Gb DDR2 SDRAM
2. Functional Description 2.1 Simplified State Diagram
CKEL
Initialization Sequence
Autorefreshing tRFC
REFSX
Selfrefresh
REFA
CKEL
Precharge PD
PD_entry CKEH ACT
FS RE
Idle
PRE
MRS
tMRD
setting MRS or EMRS
Activating tRCD WL + BL/2 + WR Writing_AP
Write_AP
tRP Precharging
RL + BL/2 + tRTP Reading_AP
Write
Read_AP
Read
Writing
PRE Rea d_A P
e_ Writ AP
Reading
CKEL
W rit e
Active PD
PD_entry CKEH
a Re
d
Automatic Sequence Command Sequence
Bank Active
This Simplified State Diagram is intended to provide a floorplan of the possible state transitions and the commands to control them. In particular situations involving more than one bank, enabling / disabling on-die termination, Power-Down entry / exit - among other things - are not captured in full detail.
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Rev. 1.02
May 2004
INFINEON Technologies
HYB18T1G400/800/160AF
1Gb DDR2 SDRAM
2.2 Basic Functionality
Read and write accesses to the DDR2 SDRAM are burst oriented; accesses start at a selected location and continue for the burst length of four or eight in a programmed sequence. Accesses begin with the registration of an Activate command, which is followed by a Read or Write command. The address bits registered coincident with the activate command are used to select the bank and row to be accessed (BA0 ~ BA2 select one of the eight banks, A0-A13 select the row for x4 and x8 components, A0~A12 select the row for x16 components). The address bits registered coincident with the Read or Write command are used to select the starting column location for the burst access and to determine if the Auto-Precharge command is to be issued. Prior to normal operation, the DDR2 SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command description and device operation. 2.2.1 Power On and Initialization DDR2 SDRAM's must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. The following sequence is required for POWER UP and Initialization.
1. Apply power and attempt to maintain CKE below 0.2 * VDDQ and ODT at a low state (all other inputs may be undefined). To guarantee ODT off, VREF must be valid and a low level must be applied to the ODT pin. Maximum power up interval for VDD/VDDQ is specified as 10.0 ms. The power interval is defined as the amount of time it takes for VDD / VDDQ to power-up from 0V to 1.8 V +/- 100 mV. - VDD,VDDL and VDDQ are driven from a single power converter output, AND - VTT is limited to 0.95 V max, AND - VREF tracks VDDQ/2 or - Apply VDD before or at the same time as VDDL, - Apply VDDL before or at the same time as VDDQ. - Apply VDDQ before or at the same time as VTT & VREF. at least one of these two sets of conditions must be met. 2. Start clock (CK, CK) and maintain stable power and clock condition for a minimum of 200 s. 3. Apply NOP or Deselect commands & take CKE high. 4. Wait minimum of 400ns, then issue a Precharge-all command. 5. Issue EMRS(2) command. (To issue EMRS(2) command, provide "low" to BA0 and BA2 and "high" to BA1) 6. Issue EMRS(3) command. (To issue EMRS(3) command, provide "low" to BA2 and "high" to BA0 and BA1) 7. Issue EMRS(1) command to enable DLL. (To issue "DLL Enable" command, provide "low" to A0 and "high" to BA0 and "low" to BA1,BA2 and A13~A15) 8. Issue MRS command (Mode Register Set) for 'DLL reset'. (To issue DLL reset command, provide "high" to A8 and "low" to BA0 ~ BA2 and A13 ~ A15) 9. Issue Precharge-all command. 10. Issue 2 or more Auto-Refresh commands. 11. Issue a MRS command with low on A8 to initialize device operation. (i.e. to program operating parameters with out resetting the DLL) 12. At least 200 clocks after step 8, execute OCD Calibration (Off Chip Driver impedance adjustment). If OCD calibration is not used, EMRS OCD Default command (A9=A8=A7=1) followed by EMRS(1) OCD Calibration Mode Exit command (A9=A8=A7=0) must be issued with other parameters of EMRS(1). 13. The DDR2 SDRAM is now ready for normal operation.
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Rev. 1.02
May 2004
INFINEON Technologies
HYB18T1G400/800/160AF
1Gb DDR2 SDRAM
Example:
CK, CK
CKE ODT "low"
400 ns
NOP
PRE ALL
tRP
tMRS
tMRS
tMRS
tMRS
MRS
PRE ALL
tRP
tRFC
1st Auto refresh
tRFC
MRS
tMRS
Follow OCD flowchart
tMRS
Any Command
EMRS(2)
EMRS(3)
EMRS(1)
2nd Auto refresh
EMRS(1) OCD
EMRS(1) OCD
min. 200 cycles to lock the DLL
Extended Mode Mode Register Register(1) Set Set with with DLL enable DLL reset Mode Register OCD Drive(1) or Set w/o DLL reset OCD default OCD calibration mode exit
2.2.2 Programming the Mode Register and Extended Mode Registers For application flexibility, burst length, burst type, CAS latency, DLL reset function, write recovery time (WR) are user defined variables and must be programmed with a Mode Register Set (MRS) command. Additionally, DLL disable function, additive CAS latency, driver impedance, ODT (On Die Termination), single-ended strobe and OCD (off chip driver impedance adjustment) are also user defined variables and must be programmed with an Extended Mode Register Set (EMRS) command. Contents of the Mode Register (MRS) and Extended Mode Registers (EMRS(#)) can be altered by re-executing the MRS and EMRS Commands. If the user chooses to modify only a subset of the MRS or EMRS variables, all variables must be redefined when the MRS or EMRS commands are issued. Also any programming of EMRS(2) or EMRS(3) must be followed by programming of MRS and EMRS(1). After initial power up, all MRS and EMRS Commands must be issued before read or write cycles may begin. All banks must be in a precharged state and CKE must be high at least one cycles before the Mode Register Set Command can be issued. Either MRS or EMRS Commands are activated by the low signals of CS, RAS, CAS and WE at the positive edge of the clock. When all bank addresses BA0 ~ BA2 are low, the DDR2 SDRAM enables the MRS command. When the bank addresses BA0 is high and BA1and BA2 are low, the DDR2 SDRAM enables the EMRS(1) command. The address input data during this cycle defines the parameters to be set as shown in the MRS and EMRS table. A new command may be issued after the mode register set command cycle time (tMRD). MRS, EMRS and DLL Reset do not affect array contents, which means reinitializazion including those can be executed any time after power-up without affecting array contents. 2.2.3 DDR2 SDRAM Mode Register Set (MRS) The mode register stores the data for controlling the various operating modes of DDR2 SDRAM. It programs CAS latency, burst length, burst sequence, test mode, DLL reset, WR (write recovery) and various vendor specific options to make DDR2 SDRAM useful for various applications. The default value of the mode register is not defined, therefore the mode register must be written after power-up for proper operation. The mode register is written by asserting low on CS, RAS, CAS, WE, BA0, BA1 and BA2, while controlling the state of address pins A0 ~ A13. The DDR2 SDRAM should be in all bank precharge with CKE already high prior to writing into the mode register. The mode register set command cycle time (tMRD) is required to complete the write operation to the mode register. The mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state. The mode register is divided into various fields depending on functionality. Burst length is defined by A0 ~ A2 with options of 4 and 8 bit burst length. Burst address sequence type is defined by A3 and CAS latency is defined by A4 ~ A6. A7 is used for test mode and must be set to low for normal MRS operation. A8 is used for DLL reset. A9 ~ A11 are used for write recovery time (WR) definition for Auto-Precharge mode. With address bit A12 two Power-Down modes can be selected, a "standard mode" and a "low-power" Power-Down mode, where the DLL is disabled. Address bit A13 and all "higher" address bits including BA0 ~ BA2 have to be set to "low" for compatibility with other DDR2 memory products with higher memory densities.
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MRS Mode Register Operation Table (Address Input For Mode Set)
BA2
BA1 BA0
A13~ A12 A11 A10 A15
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address Field
0*
0*
0*
0*
PD
WR
DLL
TM
CAS Latency
BT
Burst Length
Mode Register
A8 0 1
DLL Reset No Yes
A7 0 1
Mode Normal Test 0 1
Burst Type Sequential Interleave
A2 0 0
A1 1 1
A0 0 1
Burst Length 4 8
A12 0 1
Active Power-Down Mode Select Fast exit (use tXARD) Slow exit (use tXARDS)
A11 0 0 0 0 1 1 1 1
A10 0 0 1 1 0 0 1 1
A9 0 1 0 1 0 1 0 1
WR **) Reserved 2 3 4 5 6 Reserved Reserved
A6 0 0 0 0 1 1 1 1
A5 0 0 1 1 0 0 1 1
A4 0 1 0 1 0 1 0 1
Latency Reserved Reserved 2 (optional) ***) 3 4 5 Reserved Reserved
BA1 0 0 1 1
BA0 0 1 0 1
MRS mode MRS EMRS(1) EMRS(2): Reserved EMRS(3): Reserved
*) Must be programmed to 0 when setting the mode register. A13 ~ A15 and BA2 are reserved for future use and must be programmed to 0 when setting the mode register MRS **) The programmability of WR (Write Recovery) is for Writes with Auto-Precharge only and defines the time when the device starts precharge internally. WR must be programmed to fulfill the minimum requirement for the analogue tWR timing. ***) CAS Latency = 2 is implemented in this design, but functionality is not tested and guaranteed.
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2.2.4 DDR2 SDRAM Extended Mode Register Set (EMRS(1)) The extended mode register EMRS(1) stores the data for enabling or disabling the DLL, output driver strength, additive latency, OCD program, ODT, DQS and output buffers disable, RQDS and RDQS enable. The default value of the extended mode register EMRS(1) is not defined, therefore the extended mode register must be written after power-up for proper operation. The extended mode register is written by asserting low on CS, RAS, CAS, WE, BA1, BA2 and high on BA0, while controlling the state of the address pins. The DDR2 SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register. The mode register set command cycle time (tMRD) must be satisfied to complete the write operation to the EMRS(1). Mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in precharge state. EMRS(1) Extended Mode Register Operation Table (Address Input For Mode Set)
BA2 BA1 BA0 A13~A15 A12 A11 A10 0* 0* 1 0* Qoff RDQS DQS
A9
A8
A7
A6
Rtt
A5
A4
A3
A2
Rtt
A1
A0
Address Field Extended Mode Register
OCD program
Additive latency
D.I.C DLL
A6 A 11 R D Q S ,(R Q D S ) E na ble 0 1 A12 0 1 D is ab le E na ble Qoff a)
O utpu t bu ffers ena bled O utp ut b uffers disabled
A2 0 1 0 1
R tt (n om .) O D T d is ab led 75 ohm 150 ohm Reserved A0 0 1 D LL E na ble E na ble D is a ble
0 0 1 1
A 10 D Q S ,(R D Q S ) D isable 0 1 E n able D is a ble
A5 0 0 0 0 1 1 1 1
A4 0 0 1 1 0 0 1 1
A 3 A d ditiv eL aten c y 0 1 0 1 0 1 0 1 0 1 2 3 4 R e s erv e d R e s erv e d R e s erv e d
a) Disables DQ, DQS, DQS, RDQS, RDQS
BA1 BA0 0 0 1 1 0 1 0 1
M R S m od e MRS E M R S (1) EMRS(2) EMRS(3)
A9 0 0 0 1 1
A8 0 0 1 0 1
A7 0 1 0 0 1
O C D C alib ratio n P ro gram
OCD Cal. Mode Exit, maintain setting
D riv e (1) D rive (0) A d jus t m od e a)
OCD Calibration default b)
A1 0 1
O utp ut D riv er Im pe de nc e C o ntrol N orm a l W e ak
D riv er S iz e 10 0% 60 %
a) When Adjust mode is issued, AL from previously set value must be applied b) After setting to default, OCD mode needs to be exited by setting A9~A7 to 000. Refer to the following 2.2.2.5 section for detailed information.
*) must be programmed to 0 for compatibility with future DDR2 memory products.
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A0 is used for DLL enable or disable. A1 is used for enabling half-strength data-output driver. A2 and A6 enables ODT (On-Die termination) and sets the Rtt value. A3~A5 are used for additive latency settings and A7 ~ A9 enables the OCD impedance adjustment mode. A10 enables or disables the differential DQS and RDQS signals, A11 disables or enables RDQS. Address bit A12 have to be set to "low" for normal operation. With A12 set to "high" the SDRAM outputs are disabled and in Hi-Z. "High" on BA0 and "low" for BA1 and BA2 have to be set to access the EMRS(1). A13 and all "higher" address bits have to be set to "low" for compatibility with other DDR2 memory products with higher memory densities. Refer to the table for specific codes on the previous page. Single-ended and Differential Data Strobe Signals The following table lists all possible combinations for DQS, DQS, RDQS, RQDS which can be programmed by A10 & A11 address bits in EMRS(1). RDQS and RDQS are available in x8 components only. If RDQS is enabled in x8 components, the DM function is disabled. RDQS is active for reads and don't care for writes:
EMRS(1) A11 (RDQS Enable) 0 (Disable) 0 (Disable) 1 (Enable) 1 (Enable) A10 (DQS Enable) 0 (Enable) 1 (Disable) 0 (Enable) 1 (Disable) RDQS/DM DM DM RDQS RDQS
Stobe Function Matrix RDQS Hi-Z Hi-Z RDQS Hi-Z DQS DQS DQS DQS DQS DQS DQS Hi-Z DQS Hi-Z
Signaling
differential DQS signals single-ended DQS signals differential DQS signals single-ended DQS signals
DLL Enable/Disable The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning to normal operation after having the DLL disabled. The DLL is automatically disabled when entering Self-Refresh operation and is automatically re-enabled and reset upon exit of Self-Refresh operation. Any time the DLL is reset, 200 clock cycles must occur before a Read command can be issued to allow time for the internal clock to be synchronized with the external clock. Less clock cycles may result in a violation of the tAC or tDQSCK parameters. Output Disable (Qoff) Under normal operation, the DRAM outputs are enabled during Read operation for driving data (Qoff bit in the EMRS(1) is set to 0). When the Qoff bit is set to 1, the DRAM outputs will be disabled. Disabling the DRAM outputs allows users to measure IDD currents during Read operations, without including the output buffer current.
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2.2.5 EMRS(2) Extended Mode Register
The Extended Mode Registers EMRS(2) and EMRS(3) are reserved for future use and must be programmed when setting the mode register during initialization. The extended mode register EMRS(2) is written by asserting low on CS, RAS, CAS, WE, BA2, BA0 and high on BA1, while controlling the state of the address pins. The DDR2 SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register. The mode register set command cycle time (tMRD) must be satisfied to complete the write operation to the EMRS(2). Mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in precharge state.
BA2 BA1 BA0 A13~A15 A12 A11 A10 0* 1 0
A9
A8
A7 0*
A6
A5
A4
A3
A2
A1
A0
Address Field Extended Mode Register(2)
*) must be programmed to "0"
EMRS(2)
2.2.6 EMRS(3) Extended Mode Register
The Extended Mode Register EMRS(3) is reserved for future use and all bits except BA0 and BA1 must be programmed to 0 when setting the mode register during initialization .
BA2 BA1 BA0 A13~A15 A12 A11 A10 0* 1 1 *) must be programmed to "0" A9 A8 A7 0* A6 A5 A4 A3 A2 A1 A0 Address Field Extended Mode Register(3)
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2.3 Off-Chip Driver (OCD) Impedance Adjustment
DDR2 SDRAM supports driver calibration feature and the flow chart below is an example of the sequence. Every calibration mode command should be followed by "OCD calibration mode exit" before any other command being issued. MRS should be set before entering OCD impedance adjustment and ODT (On Die Termination) should be carefully controlled depending on system environment.
MRS should be set before entering OCD impedance adjustment and ODT should be carefully controlled depending on system environment Start EMRS: OCD calibration mode exit
EMRS: Drive (1) DQ & DQS High; DQS Low
EMRS: Drive(0) DQ & DQS Low; DQS High
ALL OK Test Need Calibration EMRS: OCD calibration mode exit
ALL OK
Test Need Calibration
EMRS: OCD calibration mode exit
EMRS : Enter Adjus t Mode
EMRS : Enter Adjust Mode
BL=4 cod e inpu t to all DQs Inc, Dec, or NOP
BL =4 code input to all DQs Inc, Dec, or NOP
EMRS: OCD calibration mode exit
EMRS: OCD calibration mode exit
EMRS: OCD calibration mode exit
End
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Extended Mode Register Set for OCD impedance adjustment OCD impedance adjustment can be done using the following EMRS(1) mode. In drive mode all outputs are driven out by DDR2 SDRAM and drive of RDQS is dependent on EMRS(1) bit enabling RDQS operation. In Drive(1) mode, all DQ, DQS (and RDQS) signals are driven high and all DQS (and RDQS) signals are driven low. In Drive(0) mode, all DQ, DQS (and RDQS) signals are driven low and all DQS (and RDQS) signals are driven high. In adjust mode, BL = 4 of operation code data must be used. In case of OCD calibration default, output driver characteristics have a nominal impedance value of 18 Ohms during nominal temperature and voltage conditions. Output driver characteristics for OCD calibration default are specified in the following table. OCD applies only to normal full strength output drive setting defined by EMRS(1) and if half strength is set, OCD default driver characteristics are not applicable. When OCD calibration adjust mode is used, OCD default output driver characteristics are not applicable. After OCD calibration is completed or driver strength is set to default, subsequent EMRS(1) commands not intended to adjust OCD characteristics must specify A7~A9 as'000' in order to maintain the default or calibrated value.
Off- Chip-Driver program A9 0 0 0 1 1 OCD impedance adjust A8 0 0 1 0 1 A7 0 1 0 0 1
Operation OCD calibration mode exit Drive(1) DQ, DQS, (RDQS) high and DQS, (RDQS) low Drive(0) DQ, DQS, (RDQS) low and DQS, (RDQS) high Adjust mode OCD calibration default
To adjust output driver impedance, controllers must issue the ADJUST EMRS(1) command along with a 4 bit burst code to DDR2 SDRAM as in the following table. For this operation, Burst Length has to be set to BL = 4 via MRS command before activating OCD and controllers must drive the burst code to all DQs at the same time. DT0 in the table means all DQ bits at bit time 0, DT1 at bit time 1, and so forth. The driver output impedance is adjusted for all DDR2 SDRAM DQs simultaneously and after OCD calibration, all DQs of a given DDR2 SDRAM will be adjusted to the same driver strength setting. The maximum step count for adjustment is 16 and when the limit is reached, further increment or decrement code has no effect. The default setting may be any step within the maximum step count range. When Adjust mode command is issued, AL from previously set value must be applied.
Off- Chip-Driver Adjust Program
4 bit burst code inputs to all DQs DT0 DT1 DT2 DT3 Operation Pull-up driver strength NOP (no operation) Increase by 1 step Decrease by 1 step NOP NOP Increase by 1 step Decrease by 1 step Increase by 1 step Decrease by 1 step Reserved Pull-down driver strength NOP (no operation) NOP NOP Increase by 1 step Decrease by 1 step Increase by 1 step Increase by 1 step Decrease by 1 step Decrease by 1 step Reserved
0 0 0 0 1 0 0 1 1
0 0 0 0 1 0 0 1 0 0 0 1 1 1 0 0 1 0 Other Combinations
0 1 0 0 0 1 0 1 0
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For proper operation of adjust mode, WL = RL - 1 = AL + CL -1 clocks and tDS / tDH should be met as the following timing diagram. Input data pattern for adjustment, DT0 - DT3 is fixed and not affected by MRS addressing mode (i.e. sequential or interleave). Burst length of 4 have to be programmed in the MRS for OCD impedance adjustment.
CK, CK
CMD
E M R S (1 )
NOP
NOP
NOP
NOP
NOP
NOP
E M R S (1 )
NOP
WL
D Q S _in
DQS
tW R
tDS tDH
D Q _ in DM DT0 DT1 DT2 DT3
OCD adjust mode
OCD calibration mode exit
Drive Mode Drive mode, both Drive(1) and Drive(0), is used for controllers to measure DDR2 SDRAM Driver impedance before OCD impedance adjustment. In this mode, all outputs are driven out tOIT after "enter drive mode" command and all output drivers are turned-off tOIT after "OCD calibration mode exit" command as the following timing diagram.
CK, CK
CMD
E M R S (1 )
NOP
NOP
NOP
NOP
E M R S (1 )
NOP
NOP
tOIT D Q S _ in
tOIT DQS high & DQS low for Drive(1), DQS low & DQS high for Drive 0 DQS high for Drive(1)
D Q _ in
DQS high for Drive(0)
Enter Drive Mode
OCD calibration mode exit
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2.5 On-Die Termination (ODT)
ODT (On-Die Termination) is a new feature on DDR2 components that allows a DRAM to turn on/off termination resistance for each DQ, DQS, DQS and DM for x4 and DQ, DQS, DQS, DM, RDQS (DM and RDQS share the same pin), and RDQS for x8 configuration via the ODT control pin, where DQS is terminated only when enabled in the EMRS(1) by address bit A10 = 0. For x8 configuration RDQS is only terminated, when enabled in the EMRS(1) by address bits A10 = 0 and A11 = 1. For x16 configuration ODT is applied to each UDQ, LDQ, UDQS, UDQS, LDQS, LDQS, UDM and LDM signal via the ODT control pin, where UDQS and LDQS are terminated only when enabled in the EMRS(1) by address bit A10 = 0. The ODT feature is designed to improve signal integrity of the memory channel by allowing the DRAM controller to independently turn on/off termination resistance for any or all DRAM devices. The ODT function can be used for all active and standby modes. ODT is turned off and not supported in SelfRefresh mode. Functional Representation of ODT
VDDQ VDDQ
sw1
sw2
Rval1 DRAM Input Buffer Rval1
Rval2 Input Pin Rval2
sw1
sw2
VSSQ
VSSQ
Switch sw1 or sw2 is enabled by the ODT pin. Selection between sw1 or sw2 is determined by "Rtt (nominal)" in EMRS(1) address bits A6 & A2. Target Rtt = 0.5 * Rval1 or 0.5 * Rval2. The ODT pin will be ignored if the Extended Mode Register (EMRS(1)) is programmed to disable ODT.
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ODT Truth Tables The ODT Truth Table shows which of the input pins are terminated depending on the state of address bit A10 and A11 in the EMRS(1) for all three device organisations (x4, x8 and x16). To activate termination of any of these pins, the ODT function has to be enabled in the EMRS(1) by address bits A6 and A2.
Input Pin EMRS(1) Address Bit A10 x4 components: DQ0~DQ3 DQS DQS DM X X 0 X x8 components: DQ0~DQ7 DQS DQS RDQS RDQS DM X X 0 X 0 X x16 components: LDQ0~LDQ7 UDQ0~UDQ7 LDQS LDQS UDQS UDQS LDM UDM X X X 0 X 0 X X X X X X X X X X X X X 1 1 0 X X X X EMRS(1) Address Bit A11
X = don't care; 0 = bit set to low; 1 = bit set to high
ODT timing modes
Depending on the operating mode synchronous or asynchronous ODT timings apply. Synchronous timings (tAOND, tAOFD, tAON and tAOF) apply for all modes, when the on-die DLL is not disabled. These modes are: Active Mode Standby Mode Fast Exit Active Power Down Mode (with MRS bit A12 is set to "0") Asynchronous ODT timings (tAOFPD, tAONPD) apply when the on-die DLL is disabled. These modes are: Slow Exit Active Power Down Mode (with MRS bit A12 is set to "1") Precharge Power Down Mode
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ODT Timing for Active and Standby (Idle) Modes
(Synchronous ODT timings)
T0
CK, CK
T1
T2
T3
T4
T5
T6
T7
T8
C K E see note 1
t IS
ODT
t IS
tAOND (2 tck)
tAOFD (2.5 tck)
DQ
tAON(min)
Rtt
tAOF(min) tAON(max) tAOF(max)
ODT01
1) Synchronous ODT timings apply for Active Mode and Standby Mode with CKE "high" and for the "Fast Exit" Active Power Down Mode (MRS bit A12 set to "0"). In all these modes the on-die DLL is enabled. 2) ODT turn-on time (tAON,min) is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max. (tAON,max) is when the ODT resistance is fully on. Both are measured from tAOND. 3) ODT turn off time min. (tAOF,min) is when the device starts to turn off the ODT resistance.ODT turn off time max. (tAOF,max) is when the bus is in high impedance. Both are measured from tAOFD.
ODT Timing for Precharge Power-Down and Active Power-Down Mode (with slow exit)
(Asynchronous ODT timings)
T0
C K, CK
T1
T2
T3
T4
T5
T6
T7
T8
CKE
"low"
t IS
ODT
t IS
tAOFPD,min tAOFPD,max tAONPD,min tAONPD,max
DQ
Rtt
ODT02
1) Asynchronous ODT timings apply for Precharge Power-Down Mode and "Slow Exit" Active Power Down Mode (MRS bit A12 set to "1"), where the on-die DLL is disabled in this mode of operation.
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ODT timing mode switch
When entering the Power Down Modes "Slow Exit" Active Power Down and Precharge Power Down two additional timing parameters (tANPD and tAXPD) define if synchronous or asynchronous ODT timings have to be applied. Mode entry: As long as the timing parameter tANPDmin is satisfied when ODT is turned on or off before entering these powerdown modes, synchronous timing parameters can be applied. If tANPDmin is not satisfied, asynchronous timing parameters apply
T-3 T1
T-5
CK, CK
T-4
T-2
T-1
T0
T2
tANPD (3 tck)
CKE
t IS
ODT turn-off, tANPD >= 3 tck :
ODT
t IS
RTT
ODT turn-off, tANPD <3 tck :
ODT
Synchronous timings apply
tAOFD
RTT
tAOFPDmax ODT turn-on, tANPD >= 3 tck :
t IS
Asynchronous timings apply
ODT
tAOND
RTT
t IS
Synchronous timings apply
ODT turn-on, tANPD < 3 tck :
ODT
tAONPDmax
RTT
ODT03
Asynchronous timings apply
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Mode exit: As long as the timing parameter tAXPDmin is satisfied when ODT is turned on or off after exiting these powerdown modes, synchronous timing parameters can be applied. If tAXPDmin is not satisfied, asynchronous timing parameters apply
T0
CK, CK
T1
T5
T6
T7
T8
T9
T10
t IS
tAXPD
CKE
ODT turn-off, tAXPD >= tAXPDmin: Synchronous timings apply
ODT
t IS
Rtt
ODT turn-off, tAXPD < tAXPDmin: Asynchronous timings apply
ODT
t IS
tAOFD
Rtt
ODT turn-on, tAXPD >= tAXPDmin: Synchronous timings apply
ODT
tAOFPDmax t IS
Rtt
t IS ODT turn-on, tAXPD < tAXPDmin: Asynchronous timings apply
ODT
tAOND
Rtt
tAONPDmax
ODT04
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2.5 Bank Activate Command
The Bank Activate command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock. The bank addresses BA0 ~ BA2 are used to select the desired bank. The row addresses A0 through A13 are used to determine which row to activate in the selected bank for x4 and x8 organised components. For x16 components row addresses A0 through A12 have to be applied. The Bank Activate command must be applied before any Read or Write operation can be executed. Immediately after the bank active command, the DDR2 SDRAM can accept a read or write command (with or without Auto-Precharge) on the following clock cycle. If a R/W command is issued to a bank that has not satisfied the tRCDmin specification, then additive latency must be programmed into the device to delay the R/W command which is internally issued to the device. The additive latency value must be chosen to assure tRCDmin is satisfied. Additive latencies of 0, 1, 2, 3 and 4 are supported. Once a bank has been activated it must be precharged before another Bank Activate command can be applied to the same bank. The bank active and precharge times are defined as tRAS and tRP, respectively. The minimum time interval between successive Bank Activate commands to the same bank is determined (tRC). The minimum time interval between Bank Active commands, to any other bank, is the Bank A to Bank B delay time (tRRD). In order to ensure that components with 8 internal memory banks do not exceed the instantaneous current supplying capability, certain restrictions on operation of the 8 banks must be observed. There are two rules. One for restricting the number of sequential Active commands that can be issued and another for allowing more time for RAS precharge for a Precharge-All command. The rules are as follows:
1) Sequential Bank Activation Restriction (JEDEC ballot item 1293.15): No more than 4 banks may be activated in a rolling tFAW window. Converting to clocks is done by deviding tFAW(ns) by tCK(ns) and rounding up to next integer value. As an example of the rolling window, if (tFAW/tCK) rounds up to 10 clocks, and an activate command is issued in clock N, no more than three further activate commands may be issued in clocks N +1 through N+9. 2) Precharge All Allowance: tRP for a Precharge-All command will equal to tRP + 1 tCK, where tRP is the value for a single bank precharge
Bank Activate Command Cycle: tRCD = 3, AL = 2, tRP = 3, tRRD = 2
T0 CK, CK
T1
T2
T3
T4
Tn
Tn+1
Tn+2
Tn+3
Internal RAS-CAS delay tRCDmin.
Address
Bank A Row Addr.
Bank A Col. Addr.
Bank B Row Addr.
Bank B Col. Addr.
Bank A Addr.
NOP
Bank B Addr.
Bank A Row Addr.
Bank A to Bank B delay tRRD. additive latency AL=2 Read A Begins Posted CAS Read B Bank A Precharge
NOP
Command
Bank A Activate
Posted CAS Read A
Bank B Activate
Bank B Precharge
Bank A Activate
tRAS Row Active Time (Bank A)
tRP Row Precharge Time (Bank A) tRC Row Cycle Time (Bank A)
ACT
tCCD
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1Gb DDR2 SDRAM
2.6 Read and Write Commands and Access Modes
After a bank has been activated, a read or write cycle can be executed. This is accomplished by setting RAS high, CS and CAS low at the clock's rising edge. WE must also be defined at this time to determine whether the access cycle is a read operation (WE high) or a write operation (WE low). The DDR2 SDRAM provides a wide variety of fast access modes. A single Read or Write Command will initiate a serial read or write operation on successive clock cycles at data rates of up to 667Mb/sec/pin for main memory. The boundary of the burst cycle is restricted to specific segments of the page length. For example, the 64Mbit x 4 I/O x 4 Bank chip has a page length of 2048 bits (defined by CA0-CA9 & CA11). In case of a 4-bit burst operation (burst length = 4) the page length of 2048 is divided into 512 uniquely addressable segments (4-bits x 4 I/O each). The 4-bit burst operation will occur entirely within one of the 512 segments (defined by CA0-CA8) beginning with the column address supplied to the device during the Read or Write Command (CA0-CA9 & A11). The second, third and fourth access will also occur within this segment, however, the burst order is a function of the starting address, and the burst sequence. In case of a 8-bit burst operation (burst length = 8) the page length of 2048 is divided into 256 uniquely addressable double segments (8-bits x 4 I/O each). The 8-bit burst operation will occur entirely within one of the 256 double segments (defined by CA0-CA7) beginning with the column address supplied to the device during the Read or Write Command (CA0-CA9 & CA11). A new burst access must not interrupt the previous 4 bit burst operation in case of BL = 4 setting. Therefore the minimum CAS to CAS delay (tCCD) is a minimum of 2 clocks for read or write cycles. For 8 bit burst operation (BL = 8) the minimum CAS to CAS delay (tCCD) is 4 clocks for read or write cycles. Burst interruption is allowed with 8 bit burst operation. For details see the "Burst Interrupt" - Section of this datasheet. Example: Read Burst Timing Example: (CL = 3, AL = 0, RL = 3, BL = 4)
T0
CK, CK
T1
T2
T3
T4
T5
T6
T7
T12
CMD
READ A
NOP
READ B
NOP
READ C
NOP
NOP
NOP
NOP
NOP
tC C D DQS, DQS
tC C D
DQ
Dout A0
Dout A1
Dout A2
Dout A3 Dout B0
Dout B1
Dout B2
Dout B3 Dout C0
Dout C1
Dout C2
Dout C3
RB
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HYB18T1G400/800/160AF
1Gb DDR2 SDRAM
2.6.1 Posted CAS Posted CAS operation is supported to make command and data bus efficient for sustainable bandwidths in DDR2 SDRAM. In this operation, the DDR2 SDRAM allows a Read or Write command to be issued immediately after the RAS bank activate command (or any time during the RAS to CAS delay time, tRCD, period). The command is held for the time of the Additive Latency (AL) before it is issued inside the device. The Read Latency (RL) is the sum of AL and the CAS latency (CL). Therefore if a user chooses to issue a Read/Write command before the tRCDmin, then AL greater than 0 must be written into the EMRS(1). The Write Latency (WL) is always defined as RL - 1 (Read Latency -1) where Read Latency is defined as the sum of Additive Latency plus CAS latency (RL=AL+CL). If a user chooses to issue a Read command after the tRCDmin period, the Read Latency is also defined as RL = AL + CL. Examples: Read followed by a write to the same bank, Activate to Read delay < tRCDmin: AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL -1) = 4, BL = 4
0
CK, CK
1
2
3
4
5
6
7
8
9
10
11
WL = RL -1 = 4 CMD DQS, DQS DQ
Activate Bank A Read Bank A Write Bank A
AL = 2 tRCD
CL = 3
RL = AL + CL = 5
Dout0 Dout1 Dout2 Dout3 Din0 Din1 Din2 Din3
PostCAS1
Read followed by a write to the same bank, Activate to Read delay < tRCDmin: AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL -1) = 4, BL = 8
0
CK, CK
1
2
3
4
5
6
7
8
9
10
11
12
WL = RL -1 = 4 CMD DQS, DQS DQ
Activate Bank A Read Bank A Write Bank A
AL = 2 tRCD
CL = 3
RL = AL + CL = 5
Dout0 Dout1 Dout2 Dout3 Dout4 Dout5 Dout6 Dout7 Din0 Din1 Din2 Din3
PostCAS3
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Read followed by a write to the same bank, Activate to Read delay = tRCDmin: AL = 0, CL = 3, RL = (AL + CL) = 3, WL = (RL -1) = 2, BL = 4
0
CK, CK
1
2
3
4
5
6
7
8
9
10
11
AL = 0 CMD DQS, DQS DQ
Activate Bank A Read Bank A Write Bank A
CL = 3 tRCD RL = AL + CL = 3
WL = RL -1 = 2
Dout0 Dout1 Dout2 Dout3
Din0
Din1
Din2
Din3
PostCAS2
Read followed by a write to the same bank, Activate to Read delay > tRCDmin: AL = 1, CL = 3, RL = 4, WL = 3, BL = 4
0
CK, CK
1
2
3
4
5
6
7
8
9
10
11
12
1
WL = 3 CMD DQS, DQS RL = 4 DQ
Dout0 Dout1 Dout2 Dout3 Din0 Din1 Din2 Din3
Activate Bank A
Read Bank A
Write Bank A
tRCD > tRCDmin.
PostCAS5
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1Gb DDR2 SDRAM
2.6.2 Burst Mode Operation Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory locations (read cycle). The parameters that define how the burst mode will operate are burst sequence and burst length. The DDR2 SDRAM supports 4 bit and 8 bit burst modes only. For 8 bit burst mode, full interleave address ordering is supported, however, sequential address ordering is nibble based for ease of implementation. The burst length is programmable and defined by the addresses A0 ~ A2 of the MRS. The burst type, either sequential or interleaved, is programmable and defined by the address bit 3 (A3) of the MRS. Seamless burst read or write operations are supported. Interruption of a burst read or write operation is prohibited, when burst length = 4 is programmed. For burst interruption of a read or write burst when burst length = 8 is used, see the "Burst Interruption" section of this datasheet. A Burst Stop command is not supported on DDR2 SDRAM devices. Burst Length and Sequence
Burst Length Starting Address (A2 A1 A0) x00 x01 4 x10 x11 000 001 010 011 8 100 101 110 111 4, 5, 6, 7, 0, 1, 2, 3 5, 6, 7, 4, 1, 2, 3, 0 6, 7, 4, 5, 2, 3, 0, 1 7, 4, 5, 6, 3, 0, 1, 2 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0 2, 3, 0, 1 3, 0, 1, 2 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 0, 5, 6, 7, 4 2, 3, 0, 1, 6, 7, 4, 5 3, 0, 1, 2, 7, 4, 5, 6 2, 3, 0, 1 3, 2, 1, 0 0, 1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4 Sequential Addressing (decimal) 0, 1, 2, 3 1, 2, 3, 0 Interleave Addressing (decimal) 0, 1, 2, 3 1, 0, 3, 2
Notes: 1) Page length is a function of I/O organization 256 Mb x 4 organization (CA0-CA9, CA11); Page Size = 1 kByte 128 Mb x 8 organization (CA0-CA9); Page Size = 1 kByte 64 Mb x 16 organization (CA0-CA9); Page Size = 2 kByte 2) Order of burst access for sequential addressing is "nibble-based" and therefore different from SDR or DDR components
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2.6.3 Burst Read Command The Burst Read command is initiated by having CS and CAS low while holding RAS and WE high at the rising edge of the clock. The address inputs determine the starting column address for the burst. The delay from the start of the command until the data from the first cell appears on the outputs is equal to the value of the read latency (RL). The data strobe output (DQS) is driven low one clock cycle before valid data (DQ) is driven onto the data bus. The first bit of the burst is synchronized with the rising edge of the data strobe (DQS). Each subsequent data-out appears on the DQ pin in phase with the DQS signal in a source synchronous manner. The RL is equal to an additive latency (AL) plus CAS latency (CL). The CL is defined by the Mode Register Set (MRS). The AL is defined by the Extended Mode Register Set (EMRS(1)). Basic Burst Read Timing
t CH
CLK CLK, CLK CLK
t CL
t CK
t DQSCK
DQS DQS, DQS DQS
t AC
t RPRE
DQ
t LZ
Dout Dout Dout
tRPST
Dout
t HZ
t DQSQmax
t QH
Examples: Burst Read Operation: RL = 5 (AL = 2, CL = 3, BL = 4)
T0
CK, CK
t DQSQmax
t QH
DO-Read
T1
T2
T3
T4
T5
T6
T7
T8
CMD
P ost C A S READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
< = tD Q S C K
DQS, DQS
AL = 2
DQ
CL = 3 RL = 5
Dout A0 Dout A1 Dout A2 Dout A3
BRead523
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Burst Read Operation: RL = 3 (AL = 0, CL = 3, BL = 8)
T0
CK, CK
T1
T2
T3
T4
T5
T6
T7
T8
CMD
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
< = tD Q S C K
DQS, DQS
CL = 3
DQ's
RL = 3
Dout A0 Dout A1 Dout A2 Dout A3 Dout A4 Dout A5 Dout A6 Dout A7
BRead303
Burst Read followed by Burst Write: RL = 5, WL = (RL-1) = 4, BL = 4
T0
CK, CK
T1
T3
T4
T5
T6
T7
T8
T9
CMD
P o ste d C A S READ A
NOP
NOP
P o ste d C A S W R IT E A
NOP
NOP
NOP
NOP
NOP
BL/2 + 2
DQS, DQS
WL = RL - 1 = 4 RL = 5
DQ
Dout A0 Dout A1 Dout A2 Dout A3 Din A0 Din A1 Din A2 Din A3
BRBW514
The minimum time from the burst read command to the burst write command is defined by a read-to-write turnaround time, which is BL/2 + 2 clocks.
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Seamless Burst Read Operation: RL = 5, AL = 2, CL = 3, BL = 4
T0
CK, CK
T1
T2
T3
T4
T5
T6
T7
T8
CMD
P o st C A S READ A
NOP
P o st C A S READ B
NOP
NOP
NOP
NOP
NOP
NOP
DQS, DQS
AL = 2
DQ
CL = 3 RL = 5
Dout A0 Dout A1 Dout A2 Dout A3 Dout B0 Dout B1 Dout B2 Dout B3
SBR523
The seamless burst read operation is supported by enabling a read command at every BL / 2 number of clocks. This operation is allowed regardless of same or different banks as long as the banks are activated.
Seamless Burst Read Operation: RL = 3, AL = 0, CL = 3, BL = 8 (non interrupting)
T0
CK, CK
T1
T2
T3
T4
T5
T6
T7
T8
T9
CMD
P ost C A S READ A
NOP
NOP
NOP
P o st C A S READ B
NOP
NOP
NOP
NOP
NO
DQS, DQS
CL = 3
DQ
RL = 3
Dout A0 Dout A1 Dout A2 Dout A3 Dout A4 Dout A5 Dout A4 Dout A7 Dout B0 Dout B1 Dout B2 Dout B3 Dou
SBR_BL8
The seamless, non interrupting 8-bit burst read operation is supported by enabling a read command at every BL / 2 number of clocks. This operation is allowed regardless of same or different banks as long as the banks are activated.
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2.6.4 Burst Write Command The Burst Write command is initiated by having CS, CAS and WE low while holding RAS high at the rising edge of the clock. The address inputs determine the starting column address. Write latency (WL) is defined by a read latency (RL) minus one and is equal to (AL + CL -1). A data strobe signal (DQS) has to be driven low (preamble) a time tWPRE prior to the WL. The first data bit of the burst cycle must be applied to the DQ pins at the first rising edge of the DQS following the preamble. The tDQSS specification must be satisfied for write cycles. The subsequent burst bit data are issued on successive edges of the DQS until the burst length is completed. When the burst has finished, any additional data supplied to the DQ pins will be ignored. The DQ signal is ignored after the burst write operation is complete. The time from the completion of the burst write to bank precharge is named "write recovery time" (tWR) and is the time needed to store the write data into the memory array. tWR is an analog timing parameter (see the AC table in this specification) and is not the programmed value for WR in the MRS. Basic Burst Write Timing
t DQSH
DQS DQS, DQS DQS
t DQSL
tWPRE
Din Din Din Din
t WPST
t DS
Example:.
t DH
Burst Write Operation: RL = 5 (AL = 2, CL = 3), WL = 4, BL = 4
T0
CK, CK
T1
T2
T3
T4
T5
T6
T7
T9
CMD
P o st C A S W R IT E A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
P re ch a rg e
<= tDQSS
DQS, DQS
C o m p le tio n o f th e B u rst W rite
WL = RL-1 = 4
DQ
DIN A0 DIN A1 DIN A2 DIN A3
tW R
BW543
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1Gb DDR2 SDRAM
Burst Write Operation: RL = 3 (AL = 0, CL = 3), WL = 2, BL = 4
T0
CK, CK
T1
T2
T3
T4
T5
T6
T7
T9
CMD
P ost C A S W R IT E A
NOP
NOP
NOP
NOP
NOP
NOP
P re ch a rg e
B ank A A ctiva te
<= tDQSS
DQS, DQS
C o m p le tio n o f th e B u rst W rite
WL = RL-1 = 2
DQ
DIN A0 DIN A1 DIN A2 DIN A3
tW R
tR P
BW322
Burst Write followed by Burst Read: RL = 5 (AL = 2, CL = 3), WL = 4, tWTR = 2, BL = 4
T0
CK, CK
T1
T2
T3
T4
T5
T6
T7
T8
T9
W rite to R e a d = (C L - 1 )+ B L /2 + tW T R (2 ) = 6
CMD
NOP NOP NOP NOP P o st C A S READ A NOP NOP NOP NOP
DQS, DQS
W L = RL - 1 = 4
DQ
DIN A0 DIN A1 DIN A2 DIN A3
AL=2 tW T R R L=5
C L=3
BWBR
The minimum number of clocks from the burst write command to the burst read command is (CL - 1) +BL/2 + tWTR where tWTR is the write-to-read turn-around time tWTR expressed in clock cycles. The tWTR is not a write recovery time (tWR) but the time required to transfer 4 bit write data from the input buffer into sense amplifiers in the array.
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Seamless Burst Write Operation: RL = 5, WL = 4, BL = 4
T0
CK, CK
T1
T2
T3
T4
T5
T6
T7
T8
CMD
P ost C A S W R IT E A
NOP
P o st C A S W R IT E B
NOP
NOP
NOP
NOP
NOP
NOP
DQS, DQS
W L = RL - 1 = 4
DQ
DIN A0 DIN A1 DIN A2 DIN A3 DIN B0 DIN B1 DIN B2 DIN B3 SBR
The seamless burst write operation is supported by enabling a write command every BL / 2 number of clocks. This operation is allowed regardless of same or different banks as long as the banks are activated.
Seamless Burst Write Operation: RL = 3, WL = 2, BL = 8, non interrupting
T0
CK, CK
T1
T2
T3
T4
T5
T6
T7
T8
CMD
W R IT E A
NOP
NOP
NOP
W R IT E B
NOP
NOP
NOP
NOP
DQS, DQS
W L = RL - 1 = 2
DQ
DIN A0 DIN A1 DIN A2 DIN A3 DIN A4 DIN A5 DIN A5 DIN A7 DIN B0 DIN B1 DIN B2 DIN B3 DIN B4 DIN B5 DIN SBW_BL8
The seamless, non interrupting 8-bit burst write operation is supported by enabling a write command at every BL / 2 number of clocks. This operation is allowed regardless of same or different banks as long as the banks are activated.
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2.6.5 Write Data Mask One write data mask input (DM) for x4 and x8 components and two write data mask inputs (LDM, UDM) for x16 components are supported on DDR2 SDRAM's, consistent with the implementation on DDR SDRAM's. It has identical timings on write operations as the data bits, and though used in a uni-directional manner, is internally loaded identically to data bits to insure matched system timing. Data mask is not used during read cycles. If DM is high during a write burst coincident with the write data, the write data bit is not written to the memory. For x8 components the DM function is disabled, when RDQS / RDQS are enabled by EMRS(1). . Write Data Mask Timing
t DQSH
DQS DQS, DQS DQS
t DQSL
t WPRE
DQ Din Din Din Din
t WPST
t DS
DM
t DH
don't care
. Burst Write Operation with Data Mask: RL = 3 (AL = 0, CL = 3), WL = 2, tWR = 3, BL = 4
T0
CK, CK
T1
T2
T3
T4
T5
T6
T7
T9
CMD
W R IT E A
NOP
NOP
NOP
NOP
NOP
NOP
P re ch a rg e
B ank A A ctiva te
<= tDQSS
DQS, DQS
WL = RL-1 = 2
DQ
DIN A0 DIN A1 DIN A2 DIN A3
tW R
tR P
DM
DM
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2.6.6 Burst Interruption Interruption of a read or write burst is prohibited for burst length of 4 and only allowed for burst length of 8 under the following conditions:
1. A Read Burst of 8 can only be interrupted by another Read command. Read burst interruption by a Write or Precharge Command is prohibited. 2. A Write Burst of 8 can only be interrupted by another Write command. Write burst interruption by a Read or Precharge Command is prohibited. 3. Read burst interrupt must occur exactly two clocks after the previous Read command. Any other Read burst interrupt timings are prohibited. 4. Write burst interrupt must occur exactly two clocks after the previous Write command. Any other Read burst interrupt timings are prohibited. 5. Read or Write burst interruption is allowed to any bank inside the DDR2 SDRAM. 6. Read or Write burst with Auto-Precharge enabled is not allowed to be interrupted. 7. Read burst interruption is allowed by a Read with Auto-Precharge command. 8. Write burst interruption is allowed by a Write with Auto-Precharge command. 9. All command timings are referenced to burst length set in the mode register. They are not referenced to the actual burst. For example, Minimum Read to Precharge timing is AL + BL/2 where BL is the burst length set in the mode register and not the actual burst (which is shorter because of interrupt). Minimum Write to Precharge timing is WL + BL/ 2 + tWR, where tWR starts with the rising clock after the un-interrupted burst end and not form the end of the actual burst end.
Examples: Read Burst Interrupt Timing Example: (CL = 3, AL = 0, RL = 3, BL = 8)
T0
CK, CK
T1
T2
T3
T4
T5
T6
T7
T8
CMD
READ A
NOP
READ B
NOP
NOP
NOP
NOP
NOP
NOP
DQS, DQS
DQ
Dout A0
Dout A1
Dout A2
Dout A3 Dout B0
Dout B1
Dout B2
Dout B3 Dout B4
Dout B5
Dout B6
Dout B
RBI
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Write Burst Interrupt Timing Example: (CL = 3, AL = 0, WL = 2, BL = 8)
T0
CK, CK
T1
T2
T3
T4
T5
T6
T7
T8
CMD
NOP
W R IT E A
NOP
W R IT E B
NOP
NOP
NOP
NOP
NOP
DQS, DQS
DQ
Din A0
Din A1
Din A2
Din A3
Din B0
Din B1
Din B2
Din B3
Dout B4
Din B5
Din B6
Din B7
WBI
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2.7 Precharge Command
The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Command is triggered when CS, RAS and WE are low and CAS is high at the rising edge of the clock. The Pre-charge Command can be used to precharge each bank independently or all banks simultaneously. Three address bits A10, BA0 ~ BA2 are used to define which bank to precharge when the command is issued. Bank Selection for Precharge by Address Bits
A10 LOW LOW LOW LOW LOW LOW LOW LOW HIGH BA0 LOW LOW HIGH HIGH LOW LOW HIGH HIGH Don't Care BA1 LOW HIGH LOW HIGH LOW HIGH LOW HIGH Don't Care BA2 LOW LOW LOW LOW HIGH HIGH HIGH HIGH Don't Care Precharge Bank(s) Bank 0 only Bank 1 only Bank 2 only Bank 3 only Bank 4 only Bank 5 only Bank 6 only Bank 7 only all banks
Note: The bank address assignment is the same for activating and precharging a specific bank.
2.7.1 Burst Read Operation Followed by a Precharge The following rules apply as long as the tRTP timing parameter - Internal Read to Precharge Command delay time - is less or equal two clocks, which is the case for operating frequencies less or equal 266 Mhz (DDR2 400 and 533 speed sorts): Minimum Read to Precharge command spacing to the same bank = AL + BL/2 clocks. For the earliest possible precharge, the precharge command may be issued on the rising edge which is "Additive Latency (AL) + BL/2 clocks" after a Read Command, as long as the minimum tRAS timing is satisfied. A new bank active command may be issued to the same bank if the following two conditions are satisfied simultaneously: (1) The RAS precharge time (tRP) has been satisfied from the clock at which the precharge begins. (2) The RAS cycle time (tRCmin) from the previous bank activation has been satisfied. For operating frequencies higher than 266 MHz, tRTP becomes > 2 clocks and one additional clock cycle has to be added for the minimum Read to Precharge command spacing, which now becomes AL + BL/2 + 1 clocks.
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Examples: Burst Read Operation Followed by Precharge: RL = 4 (AL = 1, CL = 3), BL = 4, tRTP <= 2 clocks
T0
CK, CK
T1
T2
T3
T4
T5
T6
T7
T8
CMD
P ost C A S READ A
NOP A L + B L /2 clks
NOP
P re ch a rg e
NOP tR P
NOP
B ank A A ctiva te
NOP
NOP
DQS, DQS
AL = 1 CL = 3 RL = 4
DQ
> = tR A S > = tR C > = tR T P
Dout A0
Dout A1
Dout A2
Dout A3
CL = 3
Burst Read Operation Followed by Precharge: RL = 4 (AL = 1, CL = 3), BL = 8, tRTP <= 2 clocks
T0
CK, CK
T1
T2
T3
T4
T5
T6
T7
T8
CMD
P ost C A S READ A
NOP A L + B L /2 clks
NOP
NOP
NOP
P re ch a rg e
NOP tR P
NOP
B ank A A ctiva te
DQS, DQS
AL = 1 CL = 3 RL = 4
DQ
> = tR A S > = tR C
Dout A0
Dout A1
Dout A2
Dout A3
Dout A4
Dout A5
Dout A6
Dout A7
CL = 3 > = tR T P
BR-P413(8)
first 4-bit prefetch
second 4-bit prefetch
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Burst Read Operation Followed by Precharge: RL = 5 (AL = 2, CL = 3), BL = 4, tRTP <= 2 clocks
T0
CK, CK
T1
T2
T3
T4
T5
T6
T7
T8
CMD
P o st C A S READ A
NOP A L + B L /2 clks
NOP
NOP
P re ch a rg e
NOP tR P
NOP
B ank A A ctiva te
NOP
DQS, DQS
AL = 2 RL = 5 CL = 3
DQ
> = tR A S > = tR C > = tR T P CL = 3
Dout A0
Dout A1
Dout A2
Dout A3
BR-P523
Burst Read Operation Followed by Precharge: RL = 6, (AL = 2, CL = 4), BL = 4, tRTP <= 2 clocks
T0
CK, CK
T1
T2
T3
T4
T5
T6
T7
T8
CMD
P o st C A S READ A
NOP A L + B L /2 clo cks
NOP
NOP
P re ch a rg e A
NOP tR P
NOP
NOP
B ank A A ctiva te
DQS, DQS
AL = 2 CL = 4 RL = 6
DQ
> = tR A S > = tR C > = tR T P CL = 4
Dout A0
Dout A1
Dout A2
Dout A3
BR-P624
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Burst Read Operation Followed by Precharge: RL = 4, (AL = 0, CL = 4), BL = 8, tRTP > 2 clocks
T0
CK, CK
T1
T2
T3
T4
T5
T6
T7
T8
CMD
READ A
NOP
NOP
NOP
NOP
P re ch a rg e
NOP tR P
NOP
B ank A A ctiva te
A L + B L /2 clks + 1
DQS, DQS
CL = 4 RL = 4
DQ
> = tR A S
Dout A0
Dout A1
Dout A2
Dout A3
Dout A4
Dout A5
Dout A6
Dout A7
> = tR T P
BR-P404(8)
first 4-bit prefetch
second 4-bit prefetch
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1Gb DDR2 SDRAM
2.7.2 Burst Write followed by Precharge Minimum Write to Precharge command spacing to the same bank = WL + BL/2 + tWR. For write cycles, a delay must be satisfied from the completion of the last burst write cycle until the Precharge command can be issued. This delay is known as a write recovery time (tWR) referenced from the completion of the burst write to the Precharge command. No Precharge command should be issued prior to the tWR delay, as DDR2 SDRAM does not support any burst interrupt by a Precharge command. tWR is an analog timing parameter (see the AC table in this datasheet) and is not the programmed value for tWR in the MRS. Examples:. Burst Write followed by Precharge: WL = (RL - 1) = 3, BL = 4, tWR = 3
T0
CK, CK
T1
T2
T3
T4
T5
T6
T7
T8
CMD
P ost C A S W R IT E A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
P re ch a rg e A
DQS, DQS
C o m p le tio n o f th e B u rst W rite
WL = 3
DQ
DIN A0 DIN A1 DIN A2 DIN A3
tW R
BW-P3
Burst Write followed by Precharge: WL = (RL - 1) = 4, BL = 4, tWR = 3
T0
CK, CK
T1
T2
T3
T4
T5
T6
T7
T9
CMD
P o st C A S W R IT E A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
P re ch a rg e A
DQS, DQS
C o m p le tio n o f th e B u rst W rite
WL = 4
DQ
DIN A0 DIN A1 DIN A2 DIN A3
tW R
BW-P4
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1Gb DDR2 SDRAM
2.8 Auto-Precharge Operation
Before a new row in an active bank can be opened, the active bank must be precharged using either the Precharge Command or the Auto-Precharge function. When a Read or a Write Command is given to the DDR2 SDRAM, the CAS timing accepts one extra address, column address A10, to allow the active bank to automatically begin precharge at the earliest possible moment during the burst read or write cycle. If A10 is low when the Read or Write Command is issued, then normal Read or Write burst operation is executed and the bank remains active at the completion of the burst sequence. If A10 is high when the Read or Write Command is issued, then the Auto-Precharge function is enabled. During Auto-Precharge, a Read Command will execute as normal with the exception that the active bank will begin to precharge internally on the rising edge which is CAS Latency (CL) clock cycles before the end of the read burst. Auto-Precharge is also implemented for Write Commands.The Precharge operation engaged by the Auto-Precharge command will not begin until the last data of the write burst sequence is properly stored in the memory array. This feature allows the precharge operation to be partially or completely hidden during burst read cycles (dependent upon CAS Latency) thus improving system performance for random data access. The RAS lockout circuit internally delays the Precharge operation until the array restore operation has been completed so that the Auto-Precharge command may be issued with any read or write command. 2.8.1 Burst Read with Auto-Precharge If A10 is high when a Read Command is issued, the Read with Auto-Precharge function is engaged. The DDR2 SDRAM starts an Auto-Precharge operation on the rising edge which is (AL + BL/2) cycles later from the Read with AP command if tRAS(min) and tRTP are satisfied. If tRAS(min) is not satisfied at the edge, the start point of Auto-Precharge operation will be delayed until tRAS(min) is satisfied. If tRTPmin is not satisfied at the edge, the start point of Auto-Precharge operation will be delayed until tRTPmin is satisfied. In case the internal precharge is pushed out by tRTP, tRP starts at the point where the internal precharge happens (not at the next rising clock edge after this event). So for BL = 4 the minimum time from Read with Auto-Precharge to the next Activate command becomes AL + tRTP + tRP. For BL = 8 the time from Read with Auto-Precharge to the next Activate command is AL + 2 + tRTP + tRP. Note that (tRTP + tRP) has to be rounded up to the next integer value. In any event internal precharge does not start earlier than two clocks after the last 4-bit prefetch.
A new bank active (command) may be issued to the same bank if the following two conditions are satisfied simultaneously: (1) The RAS precharge time (tRP) has been satisfied from the clock at which the Auto-Precharge begins. (2) The RAS cycle time (tRC) from the previous bank activation has been satisfied.
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Examples: Burst Read with Auto-Precharge followed by an activation to the Same Bank (tRC Limit) RL = 5 (AL = 2, CL = 3), BL = 4, tRTP <= 2 clocks
T0
CK, CK
T1
T2
T3
T4
T5
T6
T7
T8
CMD
P o ste d C A S R E A D w /A P
NOP
NOP
NOP
NOP
NOP
NOP
NOP
B ank A ctiva te
A10 ="high" AL + BL/2
DQS, DQS A u to -P re ch a rg e B e g in s
AL = 2
DQ
CL = 3 RL = 5
tRP
Dout A0 Dout A1 Dout A2 Dout A3
tRAS tRCmin.
BR-AP5231
Burst Read with Auto-Precharge followed by an Activation to the Same Bank (tRAS Limit): RL = 5 (AL = 2, CL = 3), BL = 4, tRTP <= 2 clocks
T0
CK, CK
T1
T2
T3
T4
T5
T6
T7
T8
CMD
P o s te d C A S R E A D w /A P
NOP
NOP
NOP
NOP
NOP
NOP
B ank A ctiva te
NOP
A10 ="high"
tRAS(min) DQS, DQS A u to -P re ch a rg e B e g in s
AL = 2
DQ tRC
CL = 3 RL = 5
Dout A0
tRP
Dout A1 Dout A2 Dout A3
BR-AP5232
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Burst Read with Auto-Precharge followed by an Activation to the Same Bank: RL = 4 (AL = 1, CL = 3), BL = 8, tRTP <= 2 clocks
T0
CK, CK
T1
T2
T3
T4
T5
T6
T7
T8
CMD
P o s te d C A S R E A D w /A P
NOP
NOP
NOP
NOP
NOP
NOP
NOP
B ank A ctiva te
A10 ="high"
DQS, DQS
AL + BL/2
A u to -P re ch a rg e B e g in s
tRP
AL = 1
DQ
CL = 3 RL = 4
Dout A0 Dout A1 Dout A2 Dout A3 Dout A4 Dout A5 Dout A6 Dout A7
>= tRTP
BR-AP413(8)2
first 4-bit prefetch
second 4-bit prefetch
Burst Read with Auto-Precharge followed by an Activation to the Same Bank: RL = 4 (AL = 1, CL = 3), BL = 4, tRTP > 2 clocks
T0
CK, CK
T1
T2
T3
T4
T5
T6
T7
T8
CMD
P o s te d C A S R E A D w /A P
NOP
NOP
NOP
NOP
NOP
NOP
B ank A ctiva te
NOP
A10 ="high"
DQS, DQS
AL + tRTP + tRP
A u to -P re ch a rg e B e g in s
AL = 1
DQ
CL = 3 RL = 4
Dout A0 Dout A1 Dout A2 Dout A3
tRTP
tRP
BR-AP4133
first 4-bit prefetch
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2.8.2 Burst Write with Auto-Precharge If A10 is high when a Write Command is issued, the Write with Auto-Precharge function is engaged. The DDR2 SDRAM automatically begins precharge operation after the completion of the write burst plus the write recovery time delay (WR), programmed in the MRS register, as long as tRAS is satisfied. The bank undergoing Auto-Precharge from the completion of the write burst may be reactivated if the following two conditions are satisfied. (1) The last data-in to bank activate delay time (tDAL = WR + tRP) has been satisfied. (2) The RAS cycle time (tRC) from the previous bank activation has been satisfied. In DDR2 SDRAM's the write recovery time delay (WR) has to be programmed into the MRS mode register. As long as the analog twr timing parameter is not violated, WR can be programmed between 2 and 6 clock cycles. Minimum Write to Activate command spacing to the same bank = WL + BL/2 + tDAL. Examples: Burst Write with Auto-Precharge (tRC Limit): WL = 2, tDAL = 6 (WR = 3, tRP = 3), BL = 4
T0
CK, CK
T1
T2
T3
T4
T5
T6
T7
CMD
W R IT E w /A P
NOP
NOP
NOP
NOP
NOP
NOP
NOP
B ank A A ctiva te
A10 ="high" DQS, DQS
Completion of the Burst Write
A u to -P re ch a rg e B e g in s
WL = RL-1 = 2
DQ
DIN A0 DIN A1 DIN A2 DIN A3
WR tDAL tRCmin. >=tRASmin.
tRP
BW-AP223
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Burst Write with Auto-Precharge (WR + tRP Limit): WL = 4, tDAL = 6 (WR = 3, tRP = 3), BL = 4
T0
CK, CK
T3
T4
T5
T6
T7
T8
T9
T12
CMD
P o ste d C A S W R IT E w /A P
NOP
NOP
NOP
NOP
NOP
NOP
NOP
B ank A A ctiva te
A10 ="high"
DQS, DQS
Completion of the Burst Write
A u to -P re ch a rg e B e g in s
WL = RL-1 = 4
DQ
DIN A0 DIN A1 DIN A2 DIN A3
WR tDAL >=tRC >=tRAS
tRP
BW-AP423
2.8.3 Read or Write to Precharge Command Spacing Summary
The following table summarizes the minimum command delays between Read, Read w/AP, Write, Write w/AP to the Precharge commands to the same banks and Precharge-All commands.
From Command To Command PRECHARGE (to same banks as READ) READ PRECHARGE-ALL PRECHARGE (to same banks as READ w/AP) READ w/AP PRECHARGE-ALL PRECHARGE (to same banks as WRITE) WRITE PRECHARGE-ALL PRECHARGE (to same banks as WRITE w/AP) WRITE w/AP PRECHARGE-ALL PRECHARGE (to same banks as PRECHARGE) PRECHARGE PRECHARGE-ALL PRECHARGE PRECHARGE-ALL PRECHARGE-ALL Minimum Delay between "From Command" to "To Command" AL + BL/2 + max(tRTP, 2) - 2*tck AL + BL/2 + max(tRTP, 2) - 2*tck AL + BL/2 + max(tRTP, 2) - 2*tck AL + BL/2 + max(tRTP, 2) - 2*tck WL + BL/2 + tWR WL + BL/2 + tWR WL + BL/2 + WR WL + BL/2 + WR 1*tck 1*tck 1*tck 1*tck Units tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK Notes 1, 2 1, 2 1, 2 1, 2 2 2 2 2 2 2 2 2
Note 1: RTP[cycles] = RU{tRTP(ns) / tCK(ns)}, where RU stands for round up. Note 2: For a given bank, the precharge period should be counted from the latest precharge command, either one bank precharge or precharge-all, issued to that bank. The precharge period is satisfied after tRP or tRPall depending on the latest prechargte command issued to that bank
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2.8.4 Concurrent Auto-Precharge DDR2 devices support the "Concurrent Auto-Precharge" feature. A Read with Auto-Precharge enabled, or a Write with Auto-Precharge enabled, may be followed by any command to the other bank, as long as that command does not interrupt the read or write data transfer, and all other related limitations (e.g. contention between Read data and Write data must be avoided externally and on the internal data bus. The minimum delay from a Read or Write command with Auto-Precharge enabled, to a command to a different bank, is summarized in the table below. As defined, the WL = RL - 1 for DDR2 devices which allows the command gap and corresponding data gaps to be minimized.
From Command
To Command (different bank, non-interrupting command) Read or Read w/AP
Minimum Delay with Concurrent Auto-Precharge Support (CL -1) + (BL/2) + tWTR BL/2 1 BL/2 BL/2 + 2 1
Units
Note
tCK tCK tCK tCK tCK tCK 1) 1)
WRITE w/AP
Write or Write w/AP Precharge or Activate Read or Read w/AP
Read w/AP
Write or Write w/AP Precharge or Activate
Note: 1) This rule only applies to a selective Precharge command to another banks, a Precharge-All command is illegal
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2.9 Refresh
DDR2 SDRAM requires a refresh of all rows in any rolling 64 ms interval. The necessary refresh can be generated in one of two ways: by explicit Auto-Refresh commands or by an internally timed Self-Refresh mode
2.9.1 Auto-Refresh Command
Auto-Refresh is used during normal operation of the DDR2 SDRAM's. This command is non persistent, so it must be issued each time a refresh is required. The refresh addressing is generated by the internal refresh controller. This makes the address bits 'don't care' during an Auto-Refresh command. The DDR2 SDRAM requires AutoRefresh cycles at an average periodic interval of tREFI (maximum). When CS, RAS and CAS are held low and WE high at the rising edge of the clock, the chip enters the AutoRefresh mode. All banks of the SDRAM must be precharged and idle for a minimum of the Precharge time (tRP) before the Auto-Refresh Command can be applied. An internal address counter supplies the addresses during the refresh cycle. No control of the external address bus is required once this cycle has started. When the refresh cycle has completed, all banks of the SDRAM will be in the precharged (idle) state. A delay between the Auto-Refresh Command and the next Activate Command or subsequent Auto-Refresh Command must be greater than or equal to the Auto-Refresh cycle time (tRFC). To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM, meaning that the maximum absolute interval between any Auto-Refresh command and the next Auto-Refresh command is 9 * tREFI.
T0 CK, CK
"high" CKE
T1
T2
T3
> = tRP
CMD
P re ch a rg e NOP NOP
> = t RFC
AUTO REFRESH NOP AUTO REFRESH NOP
> = t RFC
NOP ANY
AR
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2.9.2 Self-Refresh Command The Self-Refresh command can be used to retain data, even if the rest of the system is powered down. When in the Self-Refresh mode, the DDR2 SDRAM retains data without external clocking. The DDR2 SDRAM device has a built-in timer to accommodate Self-Refresh operation. The Self-Refresh Command is defined by having CS, RAS, CAS and CKE held low with WE high at the rising edge of the clock. ODT must be turned off before issuing Self Refresh command, by either driving ODT pin low or using EMRS(1) command. Once the command is registered, CKE must be held low to keep the device in Self-Refresh mode. The DLL is automatically disabled upon entering Self Refresh and is automatically enabled upon exiting Self Refresh. When the DDR2 SDRAM has entered Self-Refresh mode all of the external control signals, except CKE, are "don't care". The DRAM initiates a minimum of one Auto Refresh command internally within tCKE period once it enters Self Refresh mode. The clock is internally disabled during Self-Refresh Operation to save power. The minimum time that the DDR2 SDRAM must remain in Self Refresh mode is tCKE. The user may change the external clock frequency or halt the external clock one clock after Self-Refresh entry is registered, however, the clock must be restarted and stable before the device can exit Self-Refresh operation. The procedure for exiting Self Refresh requires a sequence of commands. First, the clock must be stable prior to CKE going back HIGH. Once Self-Refresh Exit command is registered, a delay of at least tXSNR must be satisfied before a valid command can be issued to the device to allow for any internal refresh in progress. CKE must remain high for the entire Self-Refresh exit period tXSRD for proper operation. Upon exit from Self Refresh, the DDR2 SDRAM can be put back into Self Refresh mode after tXSNR expires. NOP or deselect commands must be registered on each positive clock edge during the Self-Refresh exit interval tXSNR. ODT should be turned off during tXSRD. The use of Self Refresh mode introduces the possibility that an internally timed refresh event can be missed when CKE is raised for exit from Self Refresh mode. Upon exit from Self Refresh, the DDR2 SDRAM requires a minimum of one extra auto refresh command before it is put back into Self Refresh Mode.
T0 CK/CK T1 T2 T3 T4 T5 Tm Tn Tr
tRP* tis
CKE
tis tCKE
>=tXSRD
tis
ODT
tAOFD
>= tXSNR
CMD
S e lf R e fre sh E n try
NOP
N o n -R e a d C om m and
R ead C om m a nd
CK/CK may be halted
CK/CK must be stable
* = Device must be in the "All banks idle" state before entering Self Refresh mode. tXSRD (>=200 tCK) has to be satisfied for a Read or a Read with Auto-Precharge command. tXSNR has to be satisfied for any command except a Read or a Read with Auto-Precharge command
Since CKE is an SSTL input, VREF must be maintained during Self Refresh.
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2.10 Power-Down
Power-down is synchronously entered when CKE is registered low, along with NOP or Deselect command. CKE is not allowed to go low while mode register or extended mode register command time, or read or write operation is in progress. CKE is allowed to go low while any other operation such as row activation, Precharge, Auto-Precharge or Auto-Refresh is in progress, but power-down IDD specification will not be applied until finishing those operations. The DLL should be in a locked state when power-down is entered. Otherwise DLL should be reset after exiting power-down mode for proper read operation. DRAM design guarantees it's DLL in a locked state with any CKE intensive operations as long as DRAM controller complies with DRAM specifications. If power-down occurs when all banks are precharged, this mode is referred to as Precharge Power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as Active Power-down. For Active Power-down two different power saving modes can be selected within the MRS register, address bit A12. When A12 is set to "low" this mode is referred as "standard active power-down mode" and a fast power-down exit timing defined by the tXARD timing parameter can be used. When A12 is set to "high" this mode is referred as a power saving "low power active power-down mode". This mode takes longer to exit from the power-down mode and the tXARDS timing parameter has to be satisfied. Entering power-down deactivates the input and output buffers, excluding CK, CK, ODT and CKE. Also the DLL is disabled upon entering Precharge Power-down or slow exit active Power-down, but the DLL is kept enabled during fast exit active power-down. In power-down mode, CKE low and a stable clock signal must be maintained at the inputs of the DDR2 SDRAM, and all other input signals are "Don't Care". Power-down duration is limited by 9 times tREFI of the device. The power-down state is synchronously exited when CKE is registered high (along with a NOP or Deselect command). A valid, executable command can be applied with power-down exit latency, tXP, tXARD or tXARDS, after CKE goes high. Power-down exit latencies are defined in the AC spec table of this data sheet. Power-Down Entry Active Power-down mode can be entered after an activate command. Precharge Power-down mode can be entered after a Precharge, Precharge-All or internal precharge command. It is also allowed to enter power-mode after an Auto-Refresh command or MRS / EMRS(1) command when tMRD is satisfied. Active Power-down mode entry is prohibited as long as a Read Burst is in progress, meaning CKE should be kept high until the burst operation is finished. Therefore Active Power-Down mode entry after a Read or Read with Auto-Precharge command is allowed after RL + BL/2 is satisfied. Active Power-down mode entry is prohibited as long as a Write Burst and the internal write recovery is in progress. In case of a write command, active power-down mode entry is allowed when WL + BL/2 + tWTR is satisfied. In case of a write command with Auto-Precharge, Power-down mode entry is allowed after the internal precharge command has been executed, which is WL + BL/2 + WR starting from the write with Auto-Precharge command. In case the DDR2 SDRAM enters the Precharge Power-down mode.
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Examples: Active Power-Down Mode Entry and Exit after an Activate Command
T0
CK, CK
T1
T2
Tn
Tn+1
Tn+2
CM D
A ctiva te
NOP
NOP
NOP
NOP
NOP
V a lid C om m and
CKE
tIS tIS tXARD or tXARDS *)
Act.PD 0
Active Power-Down Entry
Active Power-Down Exit
note: Active Power-Down mode exit timing tXARD ("fast exit") or tXARDS ("slow exit") depends on the programmed state in the MRS, address bit A12.
Active Power-Down Mode Entry and Exit after a Read Command: RL = 4 (AL = 1, CL =3), BL = 4
T0
CK, CK
T1
T2
T3
T4
T5
T6
T7
T8
Tn
Tn+1
Tn+2
CMD
READ R E A D w /A P
NOP
NOP
NOP
NOP
NO P
NOP
NOP
NOP
NOP
NOP
V a lid C o m m an d
CKE DQS, DQS
tIS
RL + BL/2
tIS tXARD or tXARDS *)
Dout A0 Dout A1 Dout A2 Dout A3
AL = 1
DQ
CL = 3 RL = 4
Active Power-Down Entry
Active Power-Down Exit
Act.PD 1
note: Active Power-Down mode exit timing tXARD ("fast exit") or tXARDS ("slow exit") depends on the programmed state in the MRS, address bit A12.
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Active Power-Down Mode Entry and Exit after a Write Command: WL = 2, tWTR = 2, BL = 4
T0
CK, CK
T1
T2
T3
T4
T5
T6
T7
Tn
Tn+1
Tn+2
CMD
W R IT E
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
V a lid C o m m a nd
CKE DQS, DQS
WL + BL/2 + tWTR
tIS tIS
WL = RL - 1 = 2
DQ
DIN A0 DIN A1 DIN A2 DIN A3
tWTR
tXARD or tXARDS *)
Active Power-Down Entry
Active Power-Down Exit
Act.PD 2
note: Active Power-Down mode exit timing tXARD ("fast exit") or tXARDS ("slow exit") depends on the programmed state in the MRS, address bit A12.
Active Power-Down Mode Entry and Exit after a Write Command with AP: WL = 2, tWR = 3, BL = 4
T0
CK, CK
T1
T2
T3
T4
T5
T6
T7
Tn
Tn+1
Tn+2
CMD
W R IT E w /A P
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
V a lid C o m m a nd
CKE DQS, DQS
WL + BL/2 + WR
tIS
tIS
WL = RL - 1 = 2
DQ
DIN A0 DIN A1 DIN A2 DIN A3
WR
tXARD or tXARDS *)
Active Power-Down Entry
Active Power-Down Exit
Act.PD 3
note: Active Power-Down mode exit timing tXARD ("fast exit") or tXARDS ("slow exit") depends on the programmed state in the MRS, address bit A12.WR is the programmed value in the MRS mode register.
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Precharge Power Down Mode Entry and Exit
T0
CK, CK
T1
T2
T3
Tn
Tn+1
Tn+2
CMD
P re ch a rg e *)
NOP
NOP
NOP
NOP
NOP
NOP
V a lid C om m a nd
NOP
C KE
tIS tIS tRP
Precharge Power-Down Entry
tXP
Precharge Power-Down Exit
*) "Precharge" may be an external command or an internal precharge following Write with AP.
PrePD
Auto-Refresh command to Power-Down entry
T0
CK, CK
T1
T2
T3
T4
Tn
CMD
Auto Refresh
tRFC tXP
Valid Command
CKE
tis
CKE can go low one clock after an Auto-Refresh command When tRFC expires the DRAM is in Precharge Power-Down Mode
ARPD
MRS, EMRS command to Power-Down entry
T0
CK, CK
T1
T2
T3
T4
T5
T6
T7
CMD
MRS or EMRS
t MRD
C KE Enters Precharge Power-Down Mode
MRS_PD
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2.11 Other Commands
2.11.1 No Operation Command (NOP) The No Operation Command should be used in cases when the SDRAM is in a idle or a wait state. The purpose of the No Operation Command is to prevent the SDRAM from registering any unwanted commands between operations. A No Operation Command is registered when CS is low with RAS, CAS, and WE held high at the rising edge of the clock. A No Operation Command will not terminate a previous operation that is still executing, such as a burst read or write cycle.
2.10 Deselect Command The Deselect Command performs the same function as a No Operation Command. Deselect Command occurs when CS is brought high, the RAS, CAS, and WE signals become don't care.
2.12 Input Clock Frequency Change
During operation the DRAM input clock frequency can be changed under the following conditions: a) During Self-Refresh operation b) DRAM is in precharged power-down mode and ODT is completely turned off. The DDR2-SDRAM has to be in Precharged Power-down mode and idle. ODT must be already turned off and CKE must be at a logic "low" state. After a minimum of two clock cycles after tRP and tAOFD have been satisfied the input clock frequency can be changed. A stable new clock frequency has to be provided, before CKE can be changed to a "high" logic level again. After tXP has been satisfied a DLL RESET command via EMRS(1) has to be issued. During the following DLL re-lock period of 200 clock cycles, ODT must remain off. After the DLL-re-lock period the DRAM is ready to operate with the new clock frequency. Example: Input frequency change during Precharge Power-Down mode
T0 T1 T2 T3 T4 Tx Tx+1 Ty Ty+1 Ty+2 Ty+3 Tz
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
D LL RESET
NO P
V a lid C o m m a nd
tRP tAOFD
Minimum 2 clocks required before changing the frequency Frequency Change occurs here Stable new clock before power-down exit
tXP
200 clocks ODT is off during DLL RESET
Frequ.Ch.
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2.13 Asynchronous CKE Low Reset Event
In a given system, Asynchronous Reset event can occur at any time without prior knowledge. In this situation, memory controller is forced to drop CKE asynchronously low, immediately interrupting any valid operation. DRAM requires CKE to be maintained "high" for all valid operations as defined in this data sheet. If CKE asynchronously drops "low" during any valid operation DRAM is not guaranteed to preserve the contents of the memory array. If this event occurs, the memory controller must satisfy a time delay (tdelay) before turning off the clocks. Stable clocks must exist at the input of DRAM before CKE is raised "high" again. The DRAM must be fully re-initialized as described the initialization sequence (section 2.2.1, step 4 thru 13). DRAM is ready for normal operation after the initialization sequence. See AC timing parametric table for tdelay specification.
stable clocks
CK, CK
tdelay
CKE
CKE drops low due to an asynchronous reset event
Clocks can be turned off after this point
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3. Truth Tables
3.1 Command Truth Table
CKE Function Previous Cycle H H H L H H H H H H H H H H Current Cycle H H L H H H H H H H H X X L L Power Down Exit H L H L H H H H X H X H X X X X X 1,4 CS RAS CAS WE BA0 BA1 A13-A11 A10 BA2 BA X X X BA X BA BA BA BA BA X X X X X X X X
A9 - A0
Notes
(Extended) Mode Register Set Auto-Refresh Self-Refresh Entry Self-Refresh Exit Single Bank Precharge Precharge all Banks Bank Activate Write Write with Auto-Precharge Read Read with Auto-Precharge No Operation Device Deselect Power Down Entry
L L L H L L L L L L L L H H
L L L X L L L H H H H H X X
L L L X H H H L L L L H X X
L H H X L L H L L H H H X X
OP Code X X X L H Row Address Column Column Column Column X X X L H L H X X X Column Column Column Column X X X X X X X X
1, 2 1 1 1 1,2 1 1, 2 1,2,3 1,2,3 1,2,3 1,2,3 1 1 1,4
1. All DDR2 SDRAM commands are defined by states of CS, WE, RAS, CAS, and CKE at the rising edge of the clock. 2. Bank addresses (BA0 ~ BA2) determine which bank is to be operated upon. For (E)MRS BAx selects an (Extended) Mode Register. 3. Burst reads or writes at BL = 4 cannot be terminated. See sections "Reads interrupted by a Read" and "Writes interrupted by a Write" in section 2.4.6 for details. 4. The Power Down Mode does not perform any refresh operations. The duration of Power Down is therefore limited by the refresh requirements outlined in section 2.7. 5. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh. 6. "X" means "H or L (but a defined logic level)". 7. Operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue.
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3.2 Clock Enable (CKE) Truth Table for Synchronous Transitions
CKE Current State2 Previous Cycle 1 (N-1) L Power-Down L L Self Refresh L Bank(s) Active All Banks Idle H Any State other than listed above 1. 2. 3. 4. 5. H L H AUTOREFRESH H H H L L DESELECT or NOP DESELECT or NOP DESELECT or NOP H L DESELECT or NOP X Current Cycle 1 (N) L Command (N) 3,12 Action (N) 3 RAS, CAS, WE, CS X Maintain Power-Down Power-Down Exit Maintain Self Refresh Self Refresh Exit Active Power-Down Entry Precharge Power-Down Entry Self Refresh Entry 11, 13, 15 4, 8, 11, 13 11, 15 4, 5, 9 4,8,10,11, 13 4,8,10,11 6, 9, 11, 13 7 Notes
Refer to the Command Truth Table
6. 7. 8. 9. 10.
11. 12. 13. 14. 15. 16.
CKE (N) is the logic state of CKE at clock edge N; CKE (N-1) was the state of CKE at the previous clock edge. Current state is the state of the DDR2 SDRAM immediately prior to clock edge N. Command (N) is the command registered at clock edge N, and Action (N) is a result of Command (N). All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document. On Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the tXSNR period. Read commands may be issued only after tXSRD (200 clocks) is satisfied. Self Refresh mode can only be entered from the All Banks Idle state. Must be a legal command as defined in the Command Truth Table. Valid commands for Power-Down Entry and Exit are NOP and DESELECT only. Valid commands for Self Refresh Exit are NOP and DESELCT only. Power-Down and Self Refresh can not be entered while Read or Write operations, (Extended) mode Register operations, Precharge or Refresh operations are in progress. See section 2.8 "Power Down" and section 2.7.2 "Self Refresh Command" for a detailed list of restrictions. Minimum CKE high time is 3 clocks, minimum CKE low time is 3 clocks. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh. The Power-Down Mode does not perform any refresh operations. The duration of Power-Down Mode is therefor limited by the refresh requirements. CKE must be maintained high while the device is in OCD calibration mode. "X" means "don't care (including floating around VREF)" in Self Refresh and Power Down. However ODT must be driven high or low in Power Down if the ODT function is enabled (Bit A2 or A6 set to "1" in EMRS(1)). Operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue.
3.3 Data Mask (DM) Truth Table
Name (Function) Write Enable Write Inhibit DM L H DQs Valid X Notes 1 1
1. Used to mask write data; provided coincident with the corresponding data.
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4. Operating Conditions
4.1 Absolute Maximum Ratings
Symbol VDD VDDQ VDDL
Parameter Voltage on VDD pin relative to VSS Voltage on VDDQ pin relative to VSS Voltage on VDDL pin relative to VSS
Rating -1.0 to + 2.3 -0.5 to + 2.3 -0.5 to + 2.3 -0.5 to + 2.3 -55 to + 100
Units V V V V C
Notes
1 1 1 1 1, 2
VIN, VOUT Voltage on any pin relative to VSS TSTG Storage Temperature
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard.
4.2 DRAM Component Operating Temperature Range
Symbol TOPER
Parameter Operating Temperature
Rating 0 to 95
Units
oC
Notes
1~4
1. Operating Temperature is the case surface temperature on the center / top side of the DRAM. For measurement conditions, please refer to the JEDEC document JESD51-2. 2. The operating temperature range are the temperatures where all DRAM specification will be supported. During operation, the DRAM case temperature must be maintained between 0 - 95oC under all other specification parameters. 3. Some application may require to operate the DRAM up to 95oC case temperature. In this case above 85oC case temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 s. 4. Self-Refresh period is hard-coded in the chip and therefore it is imperative that the system ensures the DRAM is below 85oC case temperature before initiating self-refresh operation.
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5. AC & DC Operating Conditions
5.1 DC Operating Conditions
5.1.1 Recommended DC Operating Conditions (SSTL_18)
Rating Symbol VDD VDDDL VDDQ VREF VTT Parameter Min. Supply Voltage Supply Voltage for DLL Supply Voltage for Output Input Reference Voltage Termination Voltage 1.7 1.7 1.7 0.49 * VDDQ VREF - 0.04 Typ. 1.8 1.8 1.8 0.5 * VDDQ VREF Max. 1.9 1.9 1.9 0.51 * VDDQ VREF + 0.04 V V V V V 1 1 1 2, 3 4 Units Notes
1. VDDQ tracks with VDD, VDDDL tracks with VDD. AC parameters are measured with VDD, VDDQ and VDDDL tied together. 2. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ. 3. Peak to peak ac noise on VREF may not exceed +/- 2% VREF (dc). 4. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in die dc level of VREF.
5.1.2 ODT DC Electrical Characteristics
Parameter / Condition Rtt(eff) impedance value for EMRS(1)(A6,A2)=0,1; 75 ohm Rtt(eff) impedance value for EMRS(1)(A6,A2)=1,0; 150 ohm Deviation of VM with respect to VDDQ / 2 Symbol Rtt1(eff) Rtt2(eff) delta VM min. 60 120 - 6.00 nom. 75 150 max. 90 180 + 6.00
Units
Notes 1 1 2
%
1) Measurement Definition for Rtt(eff): Apply VIH(ac) and VIL(ac) to test pin separately, then measure current (VIHac) and (VILac) respectively. Rtt(eff) = (VIH(ac) - VIL(ac)) /((VIHac) - (VILac)) 2) Measurement Definition for VM: Measure voltage (VM) at test pin (midpoint) with no load: delta VM =((2* VM / VDDQ) - 1) x 100%
5.1.3 Input and Output Leakage Currents:
Symbol IIL IOL Parameter / Condition Input Leakage Current; any input 0V < VIN < VDD Output Leakage Current; 0V < VOUT < VDDQ min. -2 -5 max. +2 +5
Units
Notes 1 2

notes: 1) all other pins not under test = 0V 2) DQ's, DQS, DQS and ODT are disabled
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5.2 DC & AC Logic Input Levels DDR2 SDRAM pin timing are specified for either single ended or differential mode depending on the setting of the EMRS(1) "Enable DQS" mode bit; timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM pin timing are measured is mode dependent. In single ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at VREF. In differential mode, these timing relationships are measured relative to the crosspoint of DQS and its complement, DQS. This distinction in timing methods is verified by design and characterisatio but not subject to production test. In single ended mode, the DQS (and RDQS) signals are internally disabled and don't care. 5.2.1 Single-ended DC & AC Logic Input Levels.
Symbol VIH (dc) VIL (dc) VIH (ac) VIL (ac) Parameter DC input logic high DC input low AC input logic high AC input low Min. VREF + 0.125 - 0.3 VREF + 0.250 Max. VDDQ + 0.3 VREF - 0.125 VREF - 0.250 Units V V V V
5.2.2 Single-ended AC Input Test Conditions
Symbol VREF Condition Input reference voltage Value 0.5 * VDDQ 1.0 1.0 Units V V V / ns Notes
1, 2 1, 2 3, 4
VSWING(max) Input signal maximum peak to peak swing SLEW Input signal minimum slew rate
1. This timing and slew rate definition is valid for all single-ended signals except tis, tih, tds, tdh. 2. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device under test. 3. The input signal minimum slew rate is to be maintained over the range from VIL(dc)max to VIH(ac)min for rising edges and the range from VIH(dc)min to VIL(ac)max for falling edges as shown in the below figure. 4. AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to VIL(ac) on the negative transitions.
Start of Falling Edge Input Timing Start of Rising Edge Input Timing
VDDQ VIH(ac) min VIH(dc) min VREF VIL(dc) max VIL(ac) max VSS
VIH(ac) min - VIL(dc) max delta TR
VSWING(MAX)
delta TF Falling Slew = VIH (dc) min - V IL(ac) max delta TF
delta TR Rising Slew =
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5.2.3 Differential DC and AC Input and Output Logic Levels
Symbol VIN(dc) VID(dc) VID(ac) VIX(ac) VOX(ac)
Parameter DC input signal voltage DC differential input voltage AC differential input voltage AC differential cross point input voltage AC differential cross point output voltage
min. -0.3 0.25 0.5 0.5 * VDDQ - 0.175 0.5 * VDDQ - 0.125
max. VDDQ + 0.3 VDDQ + 0.6 VDDQ + 0.6 0.5 * VDDQ + 0.175 0.5 * VDDQ + 0.125
Units
Notes 1 2
V V V
3 4 5
notes: 1) VIN(dc) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS etc. 2) VID(dc) specifies the input differential voltage VTR - VCP required for switching. The minimum value is equal to VIH(dc) - VIL(dc). 3) VID(ac) specifies the input differential voltage VTR - VCP required for switching. The minimum value is equal to VIH(ac) - VIL(ac). 4) The value of VIX(ac) is expected to equal 0.5 x VDDQ of the transmitting device and VIX(ac) is expected to track variations in VDDQ. VIX(ac) indicates the voltage at which differential input signals must cross. 5) The value of VOX(ac) is expected to equal 0.5 x VDDQ of the transmitting device and VOX(ac) is expected to track variations in VDDQ. VOX(ac) indicates the voltage at which differential input signals must cross.
VDDQ VTR VID VIX or VOX VSSQ
SSTL18_3
Crossing Point
VCP
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5.3 Output Buffer Levels 5.3.1 SSTL_18 Output DC Current Drive
Symbol IOH IOL Parameter Output Minimum Source DC Current Output Minimum Sink DC Current SSTL_18 Class II -13.4 13.4 Units mA mA Notes
1, 3, 4 2, 3, 4
1. VDDQ = 1.7 V; VOUT = 1.42 V. (VOUT-VDDQ) / IOH must be less than 21 ohm for values of VOUT between VDDQ and VDDQ - 280 mV. 2. VDDQ = 1.7 V; VOUT = 280 mV. VOUT / IOL must be less than 21 ohm for values of VOUT between 0V and 280 mV. 3. The dc value of VREF applied to the receiving device is set to VTT 4. The values of IOH(dc) and IOL(dc) are based on the conditions given in note 1 and 2. They are used to test drive current capability to ensure VIHmin. plus a noise margin and VILmax. minus a noise margin are delivered to an SSTL_18 receiver. The actual current values are derived by shifting the desired driver operating points along 21 ohm load line to define a convenient current for measurement.
5.3.2 SSTL_18 Output AC Test Conditions
Symbol VOH VOL VOTR Parameter Minimum Required Output Pull-up Maximum Required Output Pull-down Output Timing Measurement Reference Level SSTL_18 Class II VTT + 0.603 VTT - 0.603 0.5 * VDDQ Units V V V Notes
1 1 2
1. SSTL_18 test load for VOH and VOL is different from the reference load described in section 8.1 of this datasheet. The SSTL_18 test load has a 20 Ohm series resistor additionally to the 25 Ohm termination resistor into VTT. The SSTL_18 definition assumes that +/- 335 mV must be developed across the effectively 25 Ohm termination resistor (13.4 mA x 25 Ohm = 335 mV). With an additional series resistor of 20 Ohm this translates into a minimum requirement of 603 mV swing relative to VTT, at the output device (13.4 mA * 45 Ohm) = 603 mV). 2. The VDDQ of the device under test is referenced.
5.3.3 OCD "Off-Chip Driver" Default Characteristics
Symbol
-
Description Output Impedance Pull-up / Pull down mismatch Output Impedance step size for OCD calibration Output Slew Rate
min. 12.6 0 0 1.5
nominal 18 -
max.
Unit
Notes 1,2 1, 2, 3 8 1, 4, 5, 6, 7
23.4 4 1.5 5.0
Ohms Ohms Ohms V / ns
Sout
1) VDDQ = 1.8 V 0.1 V; VDD = 1.8 V 0.1 V. 2) Impedance measurement condition for output source dc current: VDDQ = 1.7 V, VOUT = 1420 mV; (VOUT-VDDQ) / IOH must be less than 23.4 ohms for values of VOUT between VDDQ and VDDQ - 280 mV. Impedance measurement condition for output sink dc current: VDDQ = 1.7 V; VOUT = -280 mV; VOUT / IOL must be less than 23.4 ohms for values of VOUT between 0 V and 280 mV. 3) Mismatch is absolute value between pull-up and pull-down, both are measured at same temperature and voltage. 4) Slew rates measured from VIL(ac) to VIH(ac) with the load specified in Section 8.2. 5) The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as measured from AC to AC. This is verified by design and characterisation but not subject to production test. 6) DRAM output slew rate specification applies to 400, 533 and 667 MT/s speed bins. 7) Timing skew due to DRAM output slew rate mis-match between DQS / DQS and associated DQ's is included in tDQSQ and tQHS specification. 8) This represents the step size when the OCD is near 18 ohms at nominal conditions across all process parameters and represents only the DRAM uncertainty. A 0 Ohm value (no calibration) can only be achieved if the OCD impedance is 18 +/- 0.75 ohms under nominal conditions.
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5.4 Default Output V-I Characteristics DDR2 SDRAM output driver characteristics are defined for full strength default operation as selected by the EMRS(1) bits A7~A9 ='111'. Figures in Section 5.3.5 and 5.3.6 show the driver characteristics graphically and the tables sow the same data suitable for input into simulation tools. 5.4.1 Full Strength Default Pull-up Driver Characteristics
Pull-up Driver Current [mA] Voltage (V) Minimum Nominal Default low Nominal Default high Maximum
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9
-8.5 -12.1 -14.7 -16.4 -17.8 -18.6 -19.0 -19.3 -19.7 -19.9 -20.0 -20.1 -20.2 -20.3 -20.4 -20.6
-11.1 -16.0 -20.3 -24.0 -27.2 -29.8 -31.9 -33.4 -34.6 -35.5 -36.2 -36.8 -37.2 -37.7 -38.0 -38.4 -38.6
-11.8 -17.0 -22.2 -27.5 -32.4 -36.9 -40.8 -44.5 -47.7 -50.4 -52.5 -54.2 -55.9 -57.1 -58.4 -59.6 -60.8
-15.9 -23.8 -31.8 -39.7 -47.7 -55.0 -62.3 -69.4 -75.3 -80.5 -84.6 -87.7 -90.8 -92.9 -94.9 -97.0 -99.1 -101.1
The driver characteristics evaluation conditions are: Nominal Default 25oC (Tcase), VDDQ = 1.8 V, typical process Minimum 95 oC (Tcase), VDDQ = 1.7V, slow-slow process Maximum 0 oC (Tcase). VDDQ = 1.9 V, fast-fast process
0 -20
Pullup current (mA)
-40 -60 -80 -100 -120 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2
VDDQ to VOUT (V)
Minimum Nominal Default Low Nominal Default High Maximum
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5.4.2 Full Strength Default Pull-down Driver Characteristics
Pull-down Driver Current [mA] Voltage (V) Minimum Nominal Default low Nominal Default high Maximum
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9
8.5 12.1 14.7 16.4 17.8 18.6 19.0 19.3 19.7 19.9 20.0 20.1 20.2 20.3 20.4 20.6
11.3 16.5 21.2 25.0 28.3 30.9 33.0 34.5 35.5 36.1 36.6 36.9 37.1 37.4 37.6 37.7 37.9
11.8 16.8 22.1 27.6 32.4 36.9 40.9 44.6 47.7 50.4 52.6 54.2 55.9 57.1 58.4 59.6 60.9
15.9 23.8 31.8 39.7 47.7 55.0 62.3 69.4 75.3 80.5 84.6 87.7 90.8 92.9 94.9 97.0 99.1 101.1
The driver characteristics evaluation conditions are: Nominal Default 25oC (Tcase), VDDQ = 1.8 V, typical process Minimum 95 oC (Tcase), VDDQ = 1.7V, slow-slow process Maximum 0 oC (Tcase). VDDQ = 1.9 V, fast-fast process
120 Pulldown current (mA) 100 80 60 40 20 0 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 VOUT to VSSQ (V)
Minimum Nominal Default Low Nominal Default High Maximum
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5.4.3 Calibrated Output Driver V-I Characteristics DDR2 SDRAM output driver characteristics are defined for full strength calibrated operation as selected by the procedure outlined in the Off-Chip Driver (OCD) Impedance Adjustment. The following tables show the data in tabular format suitable for input into simulation tools. The nominal points represent a device at exactly 18 ohms. The nominal low and nominal high values represent the range that can be achieved with a maximum 1.5 ohms step size with no calibration error at the exact nominal conditions only (i.e. perfect calibration procedure, 1.5 ohm maximum step size guaranteed by specification). Real system calibration error needs to be added to these values. It must be understood that these V-I curves are represented here or in supplier IBIS models need to be adjusted to a wider range as a result of any system calibration error. Since this is a system specific phenomena, it cannot be quantified here. The values in the calibrated tables represent just the DRAM portion of uncertainty while looking at one DQ only. If the calibration procedure is used, it is possible to cause the device to operate outside the bounds of the default device characteristics tables and figure. In such a situation, the timing parameters in the specification cannot be guaranteed. It is solely up to the system application to ensure that the device is calibrated between the minimum and maximum default values at all times. If this can't be guaranteed by the system calibration procedure, re-calibration policy and uncertainty with DQ to DQ variation, it is recommended that only the default values to be used. The nominal maximum ad minimum values represent the change in impedance from nominal low and high as a result of voltage and temperature change from the nominal condition to the maximum and minimum conditions. If calibrated at an extreme condition, the amount of variation could be as much as from the nominal minimum to the nominal maximum or vice versa. Full Strength Calibrated Pull-down Driver Characteristics
Calibrated Pull-down Driver Current [mA] Voltage (V) Nominal Minimum (21 Ohms) Normal Low (18.75 Ohms) Nominal (18 ohms) Normal High (17.25 Ohms) Nominal Maximum (15 Ohms)
0.2 0.3 0.4
9.5 14.3 18.7
10.7 16.0 21.0
11.5 16.6 21.6
11.8 17.4 23.0
13.3 20.0 27.0
The driver characteristics evaluation conditions are: Nominal 25oC (Tcase), VDDQ = 1.8 V, typical process Nominal Low and Nominal High 25oC (Tcase), VDDQ = 1.8V, any process Nominal Minimum 95 oC (Tcase). VDDQ = 1.7 V, any process Nominal Maximum 0oC (Tcase), VDDQ = 1.9 V, any process
Full Strength Calibrated Pull-up Driver Characteristics
Calibrated Pull-up Driver Current [mA] Voltage (V) Nominal Minimum (21 Ohms) Normal Low (18.75 Ohms) Nominal (18 ohms) Normal High (17.25 Ohms) Nominal Maximum (15 Ohms)
0.2 0.3 0.4
-9.5 -14.3 -18.3
-10.7 -16.0 -21.0
-11.4 -16.5 -21.2
-11.8 -17.4 -23.0
-13.3 -20.0 -27.0
The driver characteristics evaluation conditions are: Nominal 25oC (Tcase), VDDQ = 1.8 V, typical process Nominal Low and Nominal High 25oC (Tcase), VDDQ = 1.8V, any process Nominal Minimum 95 oC (Tcase). VDDQ = 1.7 V, any process Nominal Maximum 0oC (Tcase), VDDQ = 1.9 V, any process
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5.5 Input / Output Capacitance
Symbol CCK CDCK CI CDI CIO CDIO
Parameter Input capacitance, CK and CK Input capacitance delta, CK and CK Input capacitance, all other input-only pins Input capacitance delta, all other input-only pins Input/output capacitance, DQ, DM, DQS, DQS, RDQS, RDQS Input/output capacitance delta, DQ, DM, DQS, DQS, RDQS, RDQS
min. 1.0 1.0 3.0 -
max. 2.0 0.25 2.0 0.25 4.0 0.5
Units pF pF pF pF pF pF
5.6 Power & Ground Clamp V-I Characteristics Power and Ground clamps are provided on address (A0~A13, BA0~BA2), RAS, CAS, CS, WE and ODT pins. The V-I characteristics for pins with clamps is shown in the following table:
Voltage across clamp (V) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8
Minimum Power Clamp Current (mA) 0 0 0 0 0 0 0 0 0.1 1.0 2.5 4.7 6.8 9.1 11.0 13.5 16.0 18.2 21.0
Minimum Ground Clamp Current (mA) 0 0 0 0 0 0 0 0 0.1 1.0 2.5 4.7 6.8 9.1 11.0 13.5 16.0 18.2 21.0
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6. IDD Specifications and Measurement Conditions
6.1 IDD Specifications
(VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1V, 0 oC to TCASEmax.)
-5 DDR2 -400 max. -3.7 DDR2 -533 max. -3 & -3S DDR2 -667 max. Unit
Symbol
Parameter/Condition
I/O
IDD0 IDD1
Operating Current Operating Current
x4/ x8 x16 x4/ x8 x16 all all all
MRS(12)=0 MRS(12)=1
70 75 80 90 5 35 28 13 5 40 90 105 95 110 180 7 5 2 195 255
75 80 85 95 5 46 32 17 5 50 110 130 115 135 185 7 5 2 205 270
80 85 95 105 5 56 39 21 5 60 130 155 135 165 190 7 5 2 215 285
mA mA mA mA mA mA mA mA mA
IDD2P Precharge Power-Down Current IDD2N Precharge Standby Current IDD2Q Precharge Quiet Standby Current: IDD3P Active Power-Down Standby Current IDD3N Active Standby Current IDD4R Operating Current Burst Read IDD4W Operating Current Burst Write IDD5B Burst Auto-Refresh Current (tRFC=tRFCmin) IDD5D Distributed Auto-Refresh Current (tRFC=7.8 s) IDD6 Self-Refresh Current for standard products
all all all x4/x8 x16 x4/x8 x16 all all all all x4/x8 x16
mA mA mA mA mA mA
IDD6L Self-Refresh Current for low power products IDD7 Operating Current (8 banks interleave)
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6.2 IDD Measurement Conditions
(VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1V)
Symbol IDD0 IDD1 IDD2P IDD2N IDD2Q IDD3P(0) IDD3P(1) IDD3N IDD4R IDD4W IDD5B IDD5D IDD6 Parameter/Condition Operating Current - One bank Active - Precharge tCK =tCK(IDD).; tRC = tRC(IDD); tRAS = tRASmin(IDD); CKE is HIGH, CS is HIGH between valid commands. Address and control inputs are SWITCHING; Data bus inputs are SWITCHING; Operating Current - One bank Active - Read - Precharge IOUT = 0 mA; BL = 4, tCK = tCK(IDD), tRC = tRC(IDD); tRAS = tRASmin(IDD); tRCD = tRCD(IDD), CL = CL(IDD).;AL = 0; CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING, Data bus inputs are SWITCHING; Precharge Power-Down Current: All banks idle; CKE is LOW; tCK = tCK(IDD).; Other control and address inputs are STABLE, Data Bus inputs are FLOATING. Precharge Standby Current: All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK(IDD).; Other control and address bus inputs are SWICHTING; Data bus inputs are SWITCHING. Precharge Quiet Standby Current: All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK(IDD).; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING. Active Power-Down Current: All banks open; tCK = tCK(IDD).;CKE is LOW; Other control and address inputs are STABLE; Data Bus inputs are FLOATING. MRS A12 bit is set to "0"(Fast Power-down Exit); Active Power-Down Current: All banks open; tCK = tCK(IDD).;CKE is LOW; Other control and address inputs are STABLE; Data Bus inputs are FLOATING. MRS A12 bit is set to "1"(Slow Power-down Exit); Active Standby Current: All banks open; tCK = tCK(IDD); tRAS = tRASmax(IDD).; tRP = tRP(IDD)., CKE is HIGH; CS is HIGH between valid commands; Other control and address inputs are SWITCHING; Data Bus inputs are SWITCHING. Operating Current - Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL(IDD); tCK = tCK(IDD).; tRAS = tRASmax(IDD)., tRP = tRP(IDD)., CKE is HIGH, CS is HIGH between valid commands; Address inputs are SWITCHING; Data bus inputs are SWITCHING; IOUT = 0mA. Operating Current - Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CL(IDD); tCK = tCK(IDD).; tRAS = tRASmax(IDD)., tRP = tRP(IDD).;CKE is HIGH, CS is HIGH between valid commands; Address inputs are SWITCHING; Data Bus inputs are SWITCHING; Burst Auto-Refresh Current: tCK = tCK(IDD); Refresh command every tRFC = tRFC(IDD) interval; CKE is HIGH, CS is HIGH between valid commands; Other control and address inputs are SWITCHING; Data bus inputs are SWITCHING. Distributed Auto-Refresh Current: tCK = tCK(IDD).; Refresh command every tREFI=7.8 s interval; CKE is LOW and CS is HIGH between valid commands; Other control and address inputs are SWITCHING; Data bus inputs are SWITCHING Self-Refresh Current: CKE 0.2V; external clock off, CK and CK at 0V; Other control and address inputs are FLOATING; Data Bus inputs are FLOATING. Eight Bank Interleave Read Current: 1. All banks interleaving reads, IOUT = 0 mA; BL = 4, CL=CL(IDD), AL = tRCD(IDD) -1*tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD); tFAW = tFAW(IDD); CKE is HIGH, CS is high between valid commands, Address bus inputs are STABLE during DESELECTS; Data bus is SWITCHING. 2. Timing pattern for x4 and x8 components: IDD7
- DDR2 -400: A0 RA0 A1 RA1 A2 RA2 A3 RA3 A4 RA4 A5 RA5 A6 RA6 A7 RA7 (16 clocks) - DDR2 -533: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D A4 RA4 A5 RA5 A6 RA6 A7 RA7 D D (20 clocks) - DDR2 -667: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D (26 clocks)
3. Timing pattern for x16 components:
- DDR2 -400: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D A4 RA4 A5 RA5 A6 RA6 A7 RA7 D D (20 clocks) - DDR2 -533: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D D (28 clocks) - DDR2 -667: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D (34 clocks) 4. Legend: A = Activate, RA = Read with Auto-Precharge, D=DESELECT 1. IDD specifications are tested after the device is properly initialized and IDD parameter are specified with ODT disabled. 2. Data Bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS and UDQS. 3. Definitions for IDD: LOW is defined as VIN <= VILAC(max.); HIGH is defined as VIN >= VIHAC(min.); STABLE is defined as inputs are stable at a HIGH or LOW level FLOATING is defined as inputs are VREF = VDDQ / 2 SWITCHING is defined as: Inputs are changing between HIGH and LOW every other clock (once per two clocks) for address and control signals, and inputs changing between HIGH and LOW every other data transfer (once per clock) for DQ signals not including mask or strobes. 4. Timing parameter values for IDD current measurements are defined in the following table.
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6.2 IDD Measurement Conditions (cont'd) For testing the IDD parameters, the following timing parameters are used:
-5 DDR2 -400 3-3-3 CAS Latency Clock Cycle Time Active to Read or Write delay Active to Active / Auto-Refresh command period Four Active Window Period x4 & x8 x16 x4 & x8 (1 KB page size) x16 (2 kB page size) CL(IDD) tCK(IDD) tRCD(IDD) tRC(IDD) tFAW(IDD) 3 5 15 60 37.5 50 7.5 tRRD(IDD) 10 tRASmin(IDD) tRASmax(IDD) tRP(IDD) tRFC(IDD) 45 70000 15 127.5 10 45 70000 15 127.5 10 45 70000 15 127.5 10 45 70000 12 127.5 ns ns ns ns ns -3.7 DDR2 -533 4-4-4 4 3.75 15 60 37.5 50 7.5 -3S DDR2 - 667 5-5-5 5 3 15 60 37.5 50 7.5 -3 DDR2 - 667 4-4-4 4 3 12 57 37.5 50 7.5 tCK ns ns ns ns ns ns Unit
Parameter
Symbol
Active bank A to Active bank B command delay
Active to Precharge Command Precharge Command Period Auto-Refresh to Active / Auto-Refresh command period
6.3
ODT (On Die Termination) Current
The ODT function adds additional current consumption to the DDR2 SDRAM when enabled by the EMRS(1). Depending on address bits A6 & A2 in the EMRS(1) a "week" or "strong" termination can be selected. The current consumption for any terminated input pin, depends on the input pin is in tri-state or driving "0" or "1", as long a ODT is enabled during a given period of time.
ODT current per terminated input pin:
EMRS(1) State
Enabled ODT current per DQ added IDDQ current for ODT enabled; ODT is HIGH; Data Bus inputs are FLOATING Active ODT current per DQ added IDDQ current for ODT enabled; ODT is HIGH; worst case of Data Bus inputs are STABLE or SWITCHING.
min. tbd. tbd. tbd. tbd.
typ. 6 3 12 6
max. 7.5 3.75 15 7.5
Unit mA/DQ mA/DQ mA/DQ mA/DQ
A6 = 0, A2 = 1 IODTO A6 = 1, A2 = 0 A6 = 0, A2 = 1 IODTT A6 = 1, A2 = 0
note: For power consumption calculations the ODT duty cycle has to be taken into account
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7. Electrical Characteristics & AC Timing - Absolute Specification
7.1 Timing Parameter by Speed Grade- DDR2-400 & DDR2-533
(VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1V) (notes 1-4)
-5 DDR2-400-333 min. tAC DQ output access time from CK / CK - 600 - 500 0.45 0.45 max + 600 + 500 0.55 0.55 -3.7 DDR2-533-444 min. -500 -450 0.45 0.45 max +500 +450 0.55 0.55 ps ps tCK tCK 5 ps ps ps ps ps ps tCK tCK ps ps ps ps ps 9 9 9 18 6 6 7 7 8 8
Symbol
Parameter
Unit
Notes
tDQSCK DQS output access time from CK / CK tCH tCL tHP tCK tIS tIH tDS tDH tIPW tDIPW tHZ CK, CK high-level width CK, CK low-level width Clock half period Clock cycle time Address and control input setup time Address and control input hold time DQ and DM input setup time DQ and DM input hold time Address and control input pulse width (each input) DQ and DM input pulse width (each input) Data-out high-impedance time from CK / CK CL = 3 CL = 4 & 5
min. (tCL, tCH) 5000 5000 350 475 150 275 0.6 0.35 2*tACmin tACmin tHP-tQHS WL-0.25 0.35 0.2 0.2 2 0.25 0.40 0.9 0.40 40 55 127.5 15 15 WL+0.25 0.60 1.1 0.60 70000 8000 8000 tACmax tACmax tACmax 350 450
min. (tCL, tCH) 5000 3750 250 375 100 225 0.6 0.35 2*tACmin tACmin tHP-tQHS WL-0.25 0.35 0.2 0.2 2 0.25 0.40 0.9 0.40 45 60 127.5 15 15 WL+0.25 0.60 1.1 0.60 70000 tCK tCK tCK tCK tCK tCK tCK tCK tCK ns ns ns ns ns 8000 8000 tACmax tACmax tACmax 300 400
tLZ(DQ) DQ low-impedance time from CK / CK tLZ(DQS) DQS low-impedance from CK / CK tDQSQ DQS-DQ skew (for DQS & associated DQ signals) tQHS tQH Data hold skew factor Data output hold time from DQS
tDQSS Write command to 1st DQS latching transition tDQSL,H DQS input low (high) pulse width (write cycle) tDSS tDSH tMRD DQS falling edge to CK setup time (write cycle) DQS falling edge hold time from CK (write cycle) Mode register set command cycle time
tWPRE Write preamble tWPST Write postamble tRPRE Read preamble tRPST tRAS tRC tRFC tRCD tRP Read postamble Active to Precharge command Active to Active/Auto-Refresh command period Auto-Refresh to Active/Auto-Refresh command period Active to Read or Write delay (with and without Auto-Precharge) Precharge command period (single bank)
10 9 9 11
12 13
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7.1 Timing Parameter by Speed Grade- DDR2-400 & DDR2-533
(VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1V) (notes 1-4)
-5 DDR2-400-333 min. tRP(A) tRRD Precharge-All (8 banks) command period Active bank A to Active bank B command period
x4 & x8 (1k page size) x16 (2k page size) x4 & x8 (1k page size) x16 (2k page size)
Symbol
Parameter
-3.7 DDR2-533-444 min. tRP+1tCK 7.5 10 37.5 50 2 max -
Unit
Notes
max -
tRP+1tCK 7.5 10 37.5 50 2 15 WR+tRP 10 7.5 2 6 - AL 2 200 tRFC+10 3
ns ns
22 23
ns ns ns tCK
tFAW tCCD tWR tDAL tWTR tRTP tXARD tXARDS tXP
Four Activate Window period CAS A to CAS B Command Period Write recovery time
7.8 3.9 12 -
15 WR+tRP 7.5 7.5 2 6 - AL 2 200 tRFC+10 3 0 tIS+tCK+tIH
7.8 3.9 12 -
ns tCK ns ns tCK tCK tCK tCK ns tCK s s ns ns 17 19 16 16 14 15
Auto-Precharge write recovery + precharge time Internal Write to Read command delay Internal Read to Precharge command delay Exit power down to any valid command (other than NOP or Deselect) Exit active power-down mode to Read command (slow exit, lower power) Exit precharge power-down to any valid command (other than NOP or Deselect)
tXSRD Exit Self-Refresh to Read command tXSNR Exit Self-Refresh to non-Read command tCKE tREFI tOIT CKE minimum high and low pulse width Average periodic refresh Interval OCD drive mode output delay 0oC
o
-
85oC
o
0
85 C - 95 C
Minimum time clocks remain ON after CKE asynchrotDELAY tIS+tCK+tIH nously drops LOW
Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue.
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7.2 Timing Parameter by Speed Grade - DDR2-667
(VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1V) (notes 1-4)
-3S DDR2-667-555 min. tAC DQ output access time from CK / CK -450 -400 0.45 0.45 max +450 +400 0.55 0.55 -3 DDR2-667-444 min. -450 -400 0.45 0.45 max +450 +400 0.55 0.55 ps ps tCK tCK 5 ps ps ps ps ps ps ps tCK tCK ps ps ps ps ps 9 9 9 18 7 7 8 8 6
Symbol
Parameter
Unit
Notes
tDQSCK DQS output access time from CK / CK tCH tCL tHP CK, CK high-level width CK, CK low-level width Clock half period CL = 3 tCK Clock cycle time CL = 4 CL = 5 tIS tIH tDS tDH tIPW tDIPW tHZ Address and control input setup time Address and control input hold time DQ and DM input setup time DQ and DM input hold time Address and control input pulse width (each input) DQ and DM input pulse width (each input) Data-out high-impedance time from CK / CK
min. (tCL, tCH) 5000 5000 3000 150 275 50 175 0.6 0.35 2*tACmin tACmin tHP-tQHS WL-0.25 0.35 0.2 0.2 2 0.35 0.40 0.9 0.40 45 60 127.5 15 WL+0.25 0.60 1.1 0.60 70000 8000 8000 8000 tACmax tACmax tACmax 250 350
min. (tCL, tCH) 5000 3000 3000 150 275 50 175 0.6 0.35 2*tACmin tACmin tHP-tQHS WL-0.25 0.35 0.2 0.2 2 0.35 0.40 0.9 0.40 45 57 127.5 12 WL+0.25 0.60 1.1 0.60 70000 tCK tCK tCK tCK tCK tCK tCK tCK tCK ns ns ns ns 8000 8000 8000 tACmax tACmax tACmax 250 350
tLZ(DQ) DQ low-impedance time from CK / CK tLZ(DQS) DQS low-impedance from CK / CK tDQSQ DQS-DQ skew (for DQS & associated DQ signals) tQHS tQH Data hold skew factor Data output hold time from DQS
tDQSS Write command to 1st DQS latching transition tDQSL,H DQS input low (high) pulse width (write cycle) tDSS tDSH tMRD DQS falling edge to CK setup time (write cycle) DQS falling edge hold time from CK (write cycle) Mode register set command cycle time
tWPRE Write preamble tWPST Write postamble tRPRE Read preamble tRPST tRAS tRC tRFC tRCD Read postamble Active to Precharge command Active to Active/Auto-Refresh command period Auto-Refresh to Active/Auto-Refresh command period Active to Read or Write delay (with and without Auto-Precharge)
10 9 9 11
12 13
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7.2 Timing Parameter by Speed Grade - DDR2-667
(VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1V) (notes 1-4)
-3S DDR2-667-555 min. tRP tRP(A) tRRD Precharge command period (single bank) Precharge-All (8 banks) command period Active bank A to Active bank B command period
x4 & x8 (1k page size) x16 (2k page size) x4 & x8 (1k page size) x16 (2k page size)
Symbol
Parameter
-3 DDR2-667-444 min. 12 tRP+1tCK 7.5 10 max -
Unit
Notes
max -
15 tRP+1tCK 7.5 10 37.5 50 2 15 WR+tRP 7.5 7.5 2 6 - AL 2 200 tRFC+10 3
ns ns ns 23 ns 22
tFAW tCCD tWR tDAL tWTR tRTP tXARD tXARDS tXP
Four Activate Window period CAS A to CAS B Command Period Write recovery time
-
37.5 50 2
-
ns 24 ns tCK
7.8 3.9 12 -
15 WR+tRP 7.5 7.5 2 6 - AL 2 200 tRFC+10 3 0 tIS+tCK+tIH
7.8 3.9 12 -
ns tCK tCK ns tCK tCK tCK tCK ns tCK s s ns ns 17 19 16 16 14 15
Auto-Precharge write recovery + precharge time Internal Write to Read command delay Internal Read to Precharge command delay Exit power down to any valid command (other than NOP or Deselect) Exit active power-down mode to Read command (slow exit, lower power) Exit precharge power-down to any valid command (other than NOP or Deselect)
tXSRD Exit Self-Refresh to Read command tXSNR Exit Self-Refresh to non-Read command tCKE tREFI tOIT CKE minimum high and low pulse width Average periodic refresh Interval OCD drive mode output delay 0 C - 85 C 85 C - 95 C
o o o o
0
Minimum time clocks remain ON after CKE asynchrotDELAY tIS+tCK+tIH nously drops LOW
Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue.
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7.3 ODT AC Electrical Characteristics and Operating Conditions (all speed bins)
Symbol Parameter / Condition
tAOND tAON tAONPD tAOFD tAOF tAOFPD tANPD tAXPD ODT turn-on delay -400 & -533 ODT turn-on -667 ODT turn-on (Power-Down Modes) ODT turn-off delay ODT turn-off ODT turn-off (Power-Down Modes) ODT to Power Down Mode Entry Latency ODT Power Down Exit Latency
min.
2 tAC(min) tAC(min) tAC(min) + 2 ns 2.5 tAC(min) tAC(min) + 2 ns 3 8
max.
2 tAC(max) + 1 ns tAC(max) + 0.7 ns 2 tCK + tAC(max) + 1 ns 2.5 tAC(max) + 0.6 ns 2.5 tCK + tAC(max) + 1 ns -
Units Notes
tCK ns 20
ns tCK ns ns tCK tCK 21
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7.4 Notes for Electrical Characteristics & AC Timing
1. Timings are guaranteed with CK/CK differential slew rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential slew rate of 2.0 V/ns in differential strobe mode and a slew rate of 1 V/ns in single ended mode. For other slew rates see Section 8 of this datasheet. 2. The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS,RDQS/ RDQS, input reference level is the crosspoint when in differential strobe mode; The input reference level for signals other than CK/CK, DQS / DQS, RDQS / RDQS, tIS, tiH, tDS, tDH is VREF. For tIS, tiH, tDS, tDH input reference levels see section 8.3 of this datasheet 3. Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as LOW. 4. The output timing reference voltage level is VTT. See section 8 for the reference load for timing measurements. 5. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH. 6. For input frequency change during DRAM operation, see the 2.11 section of this datasheet. 7. For timing definition, slew rate and slew rate derating see Section 8.3 8. For timing definition, slew rate and slew rate derating see Section 8.3 9. The tHZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is no longer driving (tHZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows as valid data transitions.These parameters are verified by design and characterisation, but not subject to production test. 10. The maximum limit for this parameter is not a device limit. The device operate with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 11. tRAS(max) is calculated from the maximum amount of time a DDR2 device can operate without a Refresh command which is equal to 9 * tREFI 12. A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device. 13. The tRCD timing parameter is valid for both activate command to read or write command with and without Auto-Precharge. Therefore a separate parameter tRAP for activate command to read or write command with Auto-Precharge is not necessary anymore. 14. For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to the WR parameter stored in the MRS. 15. tWTR is at least two clocks independent of operation frequency. 16. User can choose two different active power-down modes for additional power saving via MRS address bit A12. In "standard active power-down mode" (MRS, A12 = "0") a fast power-down exit timing tXARD can be used. In "low active power-down mode" (MRS, A12 ="1") a slow power-down exit timing tXARDS has to be satisfied. 17. The clock frequency is allowed to change during self-refresh mode or precharge power-down mode. In case of clock frequency change during power-down, a specific procedure is required as describes in section 2.12. 18. Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output slew rate mis-match between DQS / DQS and associated DQ in any given cycle. 19. The Auto-Refresh command interval has be reduced to 3.9 s when operating the DDR2 DRAM in a temperature range between 85oC and 95oC. 20. ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the ODT resistance is fully on. Both are measure from tAOND. 21. ODT turn off time min. is when the device starts to turn off ODT resistance ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD. 22. tRP(A) for a Precharge-All command for an 8 bank device is equal to trp + 1 * tck, where trp are the values for a single bank precharge. 23. The tRRD timing parameter depends on the page size of the DRAM organisation (see section 1.3 of the datasheet). 24. 8 bank device Sequential Activation Restriction. No more than 4 banks may be activated in a rolling tFAW window.
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8. Reference Loads, Setup & Hold Timing Definition and Slew Rate Derating
8.1 Reference Load for Timing Measurements The figure represents the timing reference load used in defining the relevant timing parameters of the device. It is not intended to either a precise representation of the typical system environment nor a depiction of the actual load presented by a production tester. System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers correlate to their production test conditions, generally a coaxial transmission line terminated at the tester electronics. This reference load is also used for output slew rate characterisation.
VDDQ DQ DQS DQS RDQS RDQS
CK, CK DUT
25 Ohm
Vtt = VDDQ / 2
Timing Reference Points
The output timing reference voltage level for single ended signals is the crosspoint with VTT. The output timing reference voltage level for differential signals is the crosspoint of the true (e.g. DQS) and the complement (e.g. DQS) signal. 8.2 Slewrate Measurements 8.2.1 Output Slewrate With the reference load for timing measurements output slew rate for falling and rising edges is measured between VTT - 250 mV and VTT + 250 mV for single ended signals.For differential signals (e.g. DQS / DQS) output slew rate is measured between DQS - DQS = - 500 mV and DQS - DQS = + 500 mV. Output slew rate is verified by design, but not subject to production test. 8.2.2 Input Slewrate - Differential signals Input slewrate for differential signals (CK / CK, DQS / DQS, RDQS / RDQS) for rising edges are measured from f.e. CK - CK = -250 mV to CK - CK = + 500 mV and from CK - CK = +250 mV to CK - CK = - 500mV for falling edges. 8.2.3 Input Slewrate - Single ended signals Input slew rate for single ended signals (other than tis, tih, tds and tdh) are measured from dc-level to ac-level: VREF -125 mV to VREF + 250 mV for rising edges and from VREF + 125 mV to VREF - 250 mV for falling edges. For slew rate definition of the input and data setup and hold parameters see section 8.3 of this datasheet.
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8.3
Input and Data Setup and Hold Time
8.3.1 Timing Definition for Input Setup (tIS) and Hold Time (tIH) Address and control input setup time (tIS) is referenced from the input signal crossing at the VIH(ac) level for a rising signal and VIL(ac) for a falling signal applied to the device under test. Address and control input hold time (tIH) is referenced from the input signal crossing at the VIL(dc) level for a rising signal and VIH(dc) for a falling signal applied to the device under test..
CK CK t IS t IH t IS t IH
V DDQ V IH(ac) min V IH(dc) min V REF V IL(dc) max V IL(ac) max V SS
8.3.2 Timing Definition for Data Setup (tDS) and Hold Time (tDH) Data input setup time (tDS) with differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at the VIH(ac) level to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the VIL(ac) level to the differential data strobe crosspoint for a falling signal applied to the device under test. DQS/DQS signals must be monotonic between VIL(dc)max and VIH(dc)min. Data input hold time (tDH) with differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at the VIL(dc) level to the differential data strobe crosspoint for a rising signal and VIH(dc) to the differential data strobe crosspoint for a falling signal applied to the device under test. DQS/DQS signals must be monotonic between VIL(dc)max and VIH(dc)min. Data input setup time (tDS) with single-ended data strobe enabled MR[bit10]=1, is referenced from the input signal crossing at the VIH(ac) level to the data strobe crossing VREF for a rising signal, and from the input signal crossing at the VIL(ac) level to the single-ended data strobe crossing VREF for a falling signal applied to the device under test. Data input hold time (tDH) with single-ended data strobe enabled MR[bit10]=1, is referenced from the input signal crossing at the VIL(dc) level to the single-ended data strobe crossing VREF for a rising signal and VIH(dc) to the single-ended data strobe crossing VREF for a falling signal applied to the device under test.
DQS DQS DQS
Differential Input Waveform Single-ended Input Waveform
V REF
t
DS
t
DH
t
t DS DH
V DDQ V IH(ac) min V IH(dc) min V REF V IL(dc) max V IL(ac) max V SS
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HYB18T1G400/800/160AF
1Gb DDR2 SDRAM
8.3.3 Slew Rate Definition for Input and Data Setup and Hold Times Setup (tIS & tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing of VIH(ac)min. Setup (tIS & tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing of VIL(ac)max. If the actual signal is always earlier than the nominal slew rate line between shaded `VREF(dc) to ac region', use nominal slew rate for derating value (see fig. A). If the actual signal is later than the nominal slew rate line anywhere between shaded `VREF(dc) to ac region', the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value.(see fig.B) Hold (tIH & tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(dc)max and the first crossing of VREF(dc). Hold (tIH & tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(dc)min and the first crossing of VREF(dc). If the actual signal is always later than the nominal slew rate line between shaded `dc to VREF region', use nominal slew rate for derating value (see fig. A). If the actual signal is earlier than the nominal slew rate line anywhere between shaded `dc to VREF(dc) region', the slew rate of a tangent line to the actual signal from the dc level to VREF level is used for derating value (see fig.B).
CK, CK for tIS and tIH DQS, DQS for tDS and tDH tIS tDS tIH tDH tIS tDS tIH tDH tIS tDS tIH tDH tIS tIH tDS tDH
CK, CK for tIS and tIH DQS, DQS for tDS and tDH
VDDQ VIH(ac)min VIH(dc)min VREF VIL(dc) max VIL(ac) max VSS
VREF to ac region dc to Vref region
VDDQ VIH(ac)min VIH(dc)min VREF
VREF to ac region dc to VREF region
dc to VREF region
dc to Vref region VREF to ac region
VREF to ac region
VIL(dc) max VIL(ac) max VSS
Delta TFS Delta TRH Delta TRS Delta TFH
Delta TFS
Delta TRH Delta TRS
Delta TFH
tangent line nominal line
Setup Slew Rate =
VREF(dc) - - VIL(ac)max VIL(dc)max VIL(ac)max Delta TFS VIH(ac)min VREF(dc) VIH(dc)min - VIL(ac)min Delta TRS VREF(dc) - VIL(dc)max VREF - VIL(dc)max Delta TRH VIH(dc)min - VREF(dc) VREF Delta TFH
falling signal
Setup Slew Rate =
tangent line [VREF(dc) - VIL(ac)max] Delta TFS tangent line [VIH(ac)min - VREF(dc)] Delta TRS tangent line [VREF(dc) - VIL(dc)max] Delta TRH tangent line [VIH(dc)min - VREF(dc)] Delta TFH
falling signal rising signal rising signal falling signal
Setup Slew Rate =
rising signal
Setup Slew Rate =
Hold Slew Rate
=
rising signal
Hold Slew Rate
=
Hold Slew Rate
=
falling signal
Hold Slew Rate
=
fig. A
fig. B
Page 83
Rev. 1.02
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INFINEON Technologies
HYB18T1G400/800/160AF
1Gb DDR2 SDRAM
8.3.4 Input Setup (tIS) and Hold (tIH) Time Derating Table
CK, CK Differential Slew Rate 2.0 V/ns
tIS tIH tIS
1.5 V/ns
tIH tIS
1.0 V/ns
tIH
Unit ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps 1. For all input signals the total tIS (input setup time) and tIH (input hold time) required is calculated by adding the individual datasheet value to the derating value listed in the previous table.
4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.25 0.2 0.15 0.1
+187 +179 +167 +150 +125 +83 0 -11 -25 -43 -67 -110 -175 -285 -350 -525 -800 -1450
+94 +89 +83 +75 +45 +21 0 -14 -31 -54 -83 -125 -188 -292 -375 -500 -708 -1125
+217 +209 +197 +180 +155 +113 +30 +19 +5 -13 -37 -80 -145 -255 -320 -495 -770 -1420
+124 +119 +113 +105 +75 +51 +30 +16 -1 -24 -53 -95 -158 -262 -345 -470 -678 -1095
+247 +239 +227 +210 +185 +143 +60 +49 +35 +17 -7 -50 -115 -225 -290 -465 -740 -1390
+154 +149 +143 +135 +105 +81 +60 +46 +29 +6 -23 -65 -128 -232 -315 -440 -648 -1065
2. For slow slewrate the total setup time might be negativ (i.e. a valid input signal will not have reached VIH(ac) / VIL(ac) at the time of the rising clock) a valid input signal is still required to complete the transistion and reach VIH(ac) / VIL(ac). For slew rates in between the values listed in the next tables, the derating values may be obtained by linear interpolation. These values are not subject to production test. They are verified only by design and characterisation.
8.3.5
Command / Address Slew rate
Data Setup (tDS) and Hold Time (tDH) Derating Tablefor differential DQS / DQS
DQS, DQS Differential Slew Rate 4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns 0.8 V/ns
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH Unit 2.0 +125 +45 +125 +45 +125 +45 ps 1.5 +83 +21 +83 +21 +83 +21 +95 +33 ps 1.0 0 0 0 0 0 0 +12 +12 +24 +24 ps 0.9 -11 -14 -11 -14 +1 -2 +13 +10 +25 +22 ps 0.8 -25 -31 -13 -19 -1 -7 +11 +5 +23 +17 ps 0.7 -31 -42 -19 -30 -7 -18 +5 -6 +17 +6 ps 0.6 -43 -49 -31 -47 -19 -35 -7 -23 +5 -11 ps 0.5 -74 -89 -62 -77 -50 -65 -38 -53 ps 0.4 -127 -140 -115 -128 -103 -116 ps 1. For all input signals the total tDS (setup time) and tDH (hold time) required is calculated by adding the individual datasheet value to the derating value listed in the previous table. 2. For slow slewrate the total setup time might be negativ (i.e. a valid input signal will not have reached VIH(ac) / VIL(ac) at the time of the rising DQS) a valid input signal is still required to complete the transistion and reach VIH(ac) / VIL(ac). For slew rates in between the values listed in the next tables, the derating values may be obtained by linear interpolation. These values are not subject to production test. They are verified only by design and characterisation.
DQ Slewrate (V/ns)
Page 84
Rev. 1.02
May 2004
INFINEON Technologies
HYB18T1G400/800/160AF
1Gb DDR2 SDRAM
8.4 Overshoot and Undershoot Specification
8.4.1 AC Overshoot / Undershoot Specification for Address and Control Pins
Parameter Maximum peak amplitude allowed for overshoot area Maximum peak amplitude allowed for undershoot area Maximum overshoot area above VDD Maximum undershoot area below VSS DDR2 -400 0.9 0.9 0.75 0.75 DDR2 -533 0.9 0.9 0.56 0.56 DDR2 -667 0.9 0.9 0.45 0.45 Units V V V.ns V.ns
Maximum Amplitude Volts (V)
Overshoot Area
VDD
VSS Undershoot Area
Maximum Amplitude Time (ns)
8.4.2 AC Overshoot / Undershoot Specification for Clock, Data, Strobe and Mask Pins
Parameter Maximum peak amplitude allowed for overshoot area Maximum peak amplitude allowed for undershoot area Maximum overshoot area above VDDQ Maximum undershoot area below VSSQ DDR2 -400 0.9 0.9 0.38 0.38 DDR2 -533 0.9 0.9 0.28 0.28 DDR2 -667 0.9 0.9 0.23 0.23 Units V V V.ns V.ns
Maximum Amplitude Volts (V)
Overshoot Area
VDDQ
VSSQ Undershoot Area
Maximum Amplitude Time (ns)
Page 85
Rev. 1.02
May 2004
INFINEON Technologies
HYB18T1G400/800/160AF
1Gb DDR2 SDRAM
9. Package Dimensions
68 balls FBGA-Package 10,0 mm x 20,0 mm MO-207 Variation DM-z (x4, x8) 92 balls FBGA-Package 10,0 mm x 20,0 mm MO-207 Variation DL-z (x16)
0,8
0,8 0,8
0,8
+ 0,05 -
0,45
20,0
16.0
+ 0,05 -
0,45
6.4
6.4
10,0
14,4
10,0
(see balls through package)
Page 86
Rev. 1.02
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INFINEON Technologies
20,0
HYB18T1G400/800/160AF
1Gb DDR2 SDRAM
10. DDR2 Component Nomenclature
1 Example: HYB
2 18
3 T
4 1G
5 40
6 0
7 A
8 C
9 -5
1 2
INFINEON Component Prefix Power Supply Voltage
HYB for DRAM Components 18 = 1.8 V Power Supply
6 7
Product Variations Die Revision
0 = standard 2 = two dies in one package A = 1st Generation B = 2nd Generation C = 3rd Generation C = BGA package F = BGA packages (lead and halogen free) -5 = DDR2-400-333 -3.7 = DDR2-533-444 -3 = DDR2-667-444 -3S = DDR2-667-555
3
DRAM Technology
T = DDR2 256 = 256 Mb 512 = 512 Mb 1G = 1024Mb 2G = 2048 Mb 40 = x4, 4 data in/outputs 80 = x8, 8 data in/outputs 16 = x16, 16 data in/outputs
8
Package Type
4
Memory Density
9
Speed Grade
5
Memory Organisation
Page 87
Rev. 1.02
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INFINEON Technologies
HYB18T1G400/800/160AF
1Gb DDR2 SDRAM
11. Content
1. Description 1.1 1.2 1.3 1.4 1.5 1.6 2. Ordering Information Pin Description DDR2 SDRAM Addressing Package Pinouts Input / Output Functional Description Block Diagrams
Functional Description 2.1 2.2 Simplified State Diagram Basic Functionality 2.2.1 Power-On and Initialization 2.2.2 Programming the Mode Registers 2.2.3 Mode Register Set (MRS) 2.2.4 Extended Mode Register Set (EMRS(1)) 2.2.5 Extended Mode Register Set (EMRS(2)) 2.2.6 Extended Mode Register Set (EMRS(3)) Off-Chip Driver (OCD) Impedance Adjustment ODT On-Die Active Termination Bank Activate Command Read and Write Command 2.6.1 Posted CAS 2.6.2 Burst Mode Operation 2.6.3 Burst Read Operation 2.6.4 Burst Write Operation 2.6.5 Write Data Mask 2.6.6 Burst Interruption Precharge Command 2.7.1 Burst Read Operation followed by a Precharge 2.7.2 Burst Write Operation followed by a Precharge Auto-Precharge Command 2.8.1 Read with Auto-Precharge 2.8.2 Write with Auto-Precharge 2.8.3 Read or Write to Precharge Command Spacing Summary 2.8.4 Concurrent Auto-Precharge Refresh Commands 2.9.1 Auto-Refresh Command 2.9.2 Self-Refresh Command Power-Down Other Commands 2.11.1 No Operation 2.11.2 Deselect Input Clock Frequency Change Asynchronous CKE Low Event
2.3 2.4 2.5 2.6
2.7 2.8
2.9 2.10 2.11 2.12 2.13 3.
Truth Tables 3.1 3.2 3.3 Command Truth Table Clock Enable (CKE) Truth Table Data Mask (DM) Truth Table
4.
Operating Conditions 4.1 4.2 Absolute Maximum Ratings DRAM Component Operating Temperature Range
Page 88
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INFINEON Technologies
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1Gb DDR2 SDRAM
Content
5. AC & DC Operation Conditions DC Operation Conditions 5.1.1 Recommended DC Operation Conditions 5.1.2 ODT DC Operation Conditions 5.1.3 Input and Output Leakage Current 5.2 DC & AC Logic Input Levels 5.2.1 Single-ended DC & AC Logic Input Levels 5.2.2 Single-ended AC Input Test Conditions 5.2.3 Differential DC and AC Input and Output Logic Levels 5.3 Output Buffer Levels 5.31 Output AC Test Conditions 5.3.2 Output DC Current Drive 5.3.5 Full Strength Pull-up Driver Characteristics 5.3.6 Full Strength Pull-down Driver Characteristics 5.3.7 Calibrated Output Driver V-I Characteristics 5.4 Input/Output Capacitances 5.5 Power & Ground Clamp V-I Characteristics 6. IDD Specifications 6.1 6.2 6.2 7. IDD Specifications IDD Measurement Conditions ODT current 5.1
AC Timing Specifications 7.1 7.2 7.3 7.4 Timing parameters by speed grade - DDR2-400 & DDR2-533 Timing parameters by speed grade - DDR2-667 ODT AC Electrical Characteristics and Operating Conditions Notes for AC Timing Specifications
8.
Reference Loads, Slew Rates and Slew Rate Derating 8.1 8.2 8.3 Reference Load for Timing Measurements Output Slew Rate Measurements Input and Data Setup and Hold Time 8.3.1 Timing Definition for Input Setup and Hold Time 8.3.2 Timing Definition for Data Setup and Hold Time 8.3.3 Slew Rate Definition for Input and Data Setup and Hold Time 8.3.4 Input Setup and Hold Time Derating Table 8.3.5 Data Setup and Hold Time Derating Table Overshoot and Undershoot Specification
8.4 9. 10.
Package Dimensions DDR2 Component Nomenclature
Page 89
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May 2004
INFINEON Technologies

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